This is the 1st May 2025 digest of SIGARCH Messages.
Call for Participation: ISCA 2025
https://www.iscaconf.org/isca2025/
Submitted by Akihiro Hayashi
52st International Symposium on Computer Architecture (ISCA 2025)
June 21–25, 2025
Tokyo, Japan, at Waseda University
The International Symposium on Computer Architecture (ISCA) is the premier forum for new ideas and experimental results in computer architecture.
ISCA is being held in Japan for the first time in 39 years, since it was last hosted in Tokyo in 1986. The program promises to be truly exciting, featuring not only forward-looking and novel technical paper presentations, but also a panel session with ISCA legends and a total of 33 tutorials and workshops.
We warmly invite you to join us!
Registration for the conference is now open at: https://www.iscaconf.org/isca2025/attend/register.php
(Early Registration Deadline: 11:59pm AoE, May 22, 2025)
For those of you requiring a Visa we strongly encourage to start the process as soon as possible.
Visa information is now available at: https://www.iscaconf.org/isca2025/attend/visa.php
For more details on ISCA 2025, please visit the main conference website at:
https://iscaconf.org/isca2025/
Call for Papers: MEMOCODE 2025
https://memocode2025.github.io/
Submitted by Geovani Benita
MEMCODE 2025 – 23rd ACM/IEEE International Symposium on Formal Methods and Models for System Design (FMCPS)
Part of ESWEEK 2025
October 02-03, 2025, TAIPEI, TAIWAN
MEMOCODE, originally a forum on methods and models for hardware-software codesign, has become a privileged forum to discuss on formal methods and models for the design of cyber-physical system and the verification of its safety and security requirements (FMCPS).
MEMOCODE’25 is a part of ESWEEK 2025, which will take place in Taipei, Taiwan. Registered attendees can attend sessions in any of the online events, including the conferences (CASES, CODES+ISSS, EMSOFT), symposia, tutorials, workshops, and education classes.
https://memocode2025.github.io/
https://esweek.org/memocode/
Selected accepted papers will be invited to extend their accepted papers for a special edition in a journal such as the ACM Transactions on Embedded Computing Systems (ACM TECS). See more on this at the end of this CFP.
Topics of interest
MEMOCODE solicits research papers on formal methods in system design that address the foundations, engineering methods, tools, or experimental case studies. Research areas of interest include, but are not limited to, the following:
Important Dates
Abstract submission deadline: April 28, 2025 May 8, 2025
Paper submission deadline: May 5, 2025 May 5, 2025
Notification of acceptance: Jul 8, 2025
Final version of papers: August 11, 2025
Submissions
MEMOCODE’25 calls for three kinds of submissions: regular papers, late-breaking results, and tool presentations. All papers must be written in English and formatted according to the ACM Sigconf style conference template. A double-blind review process will be enforced. Authors must not reveal their identity directly or indirectly. Submission of papers is handled via HotCRP.
For questions regarding technical submissions, feel free to contact one of the program committee co-chairs. All accepted papers (regular papers, late-breaking results, and tool papers) will be submitted for inclusion in ACM Digital Library. Publication in the proceedings is contingent on one author registering for and presenting the paper at the conference.
Outstanding Paper Award
A selection of papers will be recognized as outstanding papers and will be highlighted on the symposium website.
Special Edition for Journal
Selected accepted papers will be invited to extend their accepted papers (at least 30% extension over the accepted version) for a special edition in a journal such as the ACM Transactions on Embedded Computing Systems (ACM TECS) or Leibniz Transactions on Embedded Systems (LITES). Kindly follow the call for submissions for the special edition to check the relevant deadlines and timeline of the review process. Note that the extended version of the paper will go through a separate review process in the journal.
Organizing committee
General Chairs:
Claire Pagetti, ONERA, France
Nan Guan, City University of Hong Kong
Program Chairs:
Srinivas Pinisetty, Indian Institute of Technology Bhubaneswar, India
Sudipta Chattopadhyay, Singapore University of Technology and Design
Keynote Speakers:
Sanjay Lall, Stanford University
Naijun Zhan, Peking University
Call for Papers: IISWC 2025
https://iiswc.org/iiswc2025/cfp.html
Submitted by Dmitrii Ustiugov
IEEE International Symposium on Workload Characterization (IISWC) 2025
Overview:
IISWC invites manuscripts that present original, unpublished research in all areas related to the characterization and analysis of computing system workloads, including translational research related to production-oriented commercial systems. Work focusing on emerging technologies and interdisciplinary work are especially welcome.
Important Deadlines:
Paper Submission: June 21, 2025
Rebuttal Period: July 24, 2025 – July 31, 2025
Author Notification: August 12, 2025
Camera-ready Deadline: September 1, 2025
Submission Guidelines:
Topics:
For full details, submission guidelines, and artifact evaluation information, please visit the conference website.
Call for Papers: PACT 2025
http://wikicfp.com/cfp/servlet/event.showcfp?eventid=185980
Submitted by Rio Yokota
The International Conference on Parallel Architectures and Compilation Techniques (PACT) 2025
Irvine, California, USA
November 3-6, 2025.
Submission Site: https://pact25.hotcrp.com
Scope
The International Conference on Parallel Architectures and Compilation Techniques (PACT) is a unique technical conference at the intersection of hardware and software, with a special emphasis on parallelism. PACT brings together researchers from computer architectures, compilers, execution environments, programming languages, and applications to present and discuss their latest research results, tools, and practical experiences.
PACT seeks submissions in two categories:
– Research Papers
– Tools and Practical Experience (TPE) Papers
Research Papers
Research papers will be evaluated by the PACT Program Committee based on:
– Relevance: The paper should align with PACT’s topics of interest.
– Novelty/Originality: The work should present new ideas or offer fresh perspectives.
– Significance: The research should address an important problem and have the potential to influence future work.
– Results: The claims should be well-supported by clear and validated results.
– Comparison to Prior Work: The paper should properly discuss existing literature, highlighting similarities, differences, and improvements.
Tools and Practical Experience (TPE) Papers
TPE papers focus on practical applications, industry challenges, and experience reports. A TPE paper must clearly explain its functionality, summarize practical experience with realistic case studies, and describe any supporting artifacts. The title of a TPE paper must include the prefix “TPE:”. TPE papers follow the same submission guidelines and are reviewed by the same Program Committee as research papers.
TPE papers will be evaluated based on:
– Originality: They should present PACT-related technologies applied to real-world problems.
– Usability: The tool or software should have broad applicability and aid PACT-related research.
– Documentation: The tool/software should be well-documented on a public website.
– Benchmark Repository: A benchmark suite should be provided for testing.
– Availability: Preference is given to tools/software that are freely available, though industry/commercial tools may be considered with justification.
– Foundations: The paper should relate to PACT’s principles, though extensive theoretical discussion is not required.
Topics of Interest
PACT welcomes submissions on topics including, but not limited to:
– Parallel architectures, including accelerators for AI and other domains
– Compilers and tools for parallel architectures
– Applications and experimental studies of parallel processing
– Computational models for concurrent execution
– Multicore, multithreaded, superscalar, and VLIW architectures
– Compiler and hardware support for reducing memory latencies
– Support for correctness in hardware and software
– Reconfigurable parallel computing
– Dynamic translation and optimization
– I/O issues in parallel computing and their application impact
– Parallel programming languages, algorithms, and applications
– Middleware and runtime system support for parallel computing
– Application-specific parallel systems
– Distributed computing architectures and systems
– Heterogeneous systems leveraging various accelerators
– In-core and in-chip accelerators and their optimization
– Applications of machine learning to parallel computing
– Large-scale data processing, including in-memory computing accelerators
– Insights from modern parallel applications for architecture and compiler design
– Neuromorphic computing as both an application and a tool for architectures and compilers
– Quantum computing architectures and compilers
Submission Guidelines
Ensure that your submission meets the following requirements:
– Format: Papers are limited to 10 pages (excluding references) in ACM 8.5” x 11” format, double-column, 9pt font (e.g., using the `sigconf` LaTeX template). The text box must not exceed 7.15” x 9” (18.2cm x 22.9cm). Templates are available on the ACM Author Gateway (https://authors.acm.org/proceedings/production-information/taps-production-workflow).
– Abstract: Papers must include an abstract of under 300 words.
– Originality: Submissions must contain original material not previously published or under review elsewhere. Material presented at workshops without copyrighted proceedings may be submitted.
– TPE Papers: Must be prefixed with “TPE:” in the title.
– Double-Blind Review: The review process is double-blind to prevent bias. Submissions must not include author names, affiliations, or self-references that reveal authorship. Prior work by the authors must be cited in the third person.
– Legibility: Figures and graphs must be readable without magnification.
– Submission Format: Papers must be submitted in PDF format.
– Supplementary Material: A single anonymized PDF may be uploaded with additional proofs, results, or datasets. Reviewers are not required to consult supplementary material.
Posters:
– Poster submissions must follow the same formatting guidelines but are limited to 2 pages.
– Papers not accepted for full presentation will automatically be considered for posters unless authors opt out in their abstract submission.
– Two-page poster summaries will be included in the conference proceedings.
Artifact Evaluation
Authors of accepted papers are encouraged to submit their artifacts for evaluation. The Artifact Evaluation Committee assesses availability, functionality, and reproducibility. Successful artifacts will receive a seal of approval in the published paper. Authors can include a 2-page Artifact Appendix in the final paper.
We encourage authors to use open-source frameworks such as Docker, OCCAM, reprozip, CodeOcean, and Collective Knowledge to improve artifact portability and reproducibility.
Camera-Ready Instructions
– Page Limit: The final version must not exceed 11 pages, with an optional 2-page Artifact Appendix.
– Extra Pages: Up to 2 additional pages may be purchased for $200 per page.
Important Dates
– Abstract Submission Deadline: April 11, 2025 April 18, 2025 (Deadline extended)
– Paper Submission Deadline: April 18, 2025 April 25, 2025 (Deadline extended)
– Rebuttal Period: June 24-27, 2025
– Author Notification: July 28, 2025
– Artifact Submission: August 8, 2025
– Camera-Ready Deadline: September 15, 2025
All deadlines are firm at midnight anywhere on Earth (AoE).
We look forward to your submissions!
Call for Papers: PAW-ATM 2025: Parallel Applications Workshop, Alternatives To MPI+X
https://sourceryinstitute.github.io/PAW/
Submitted by Karla Vanessa Morris Wright
PAW-ATM 2025: Parallel Applications Workshop, Alternatives To MPI+X
Held in conjunction with SC25, St. Louis, MO
https://sourceryinstitute.github.io/PAW/
Summary
As supercomputers become more and more powerful, the number and diversity of applications that can be tackled with these machines grow. Unfortunately, the architectural complexity of these supercomputers grows as well, with heterogeneous processors, multiple levels of memory hierarchy, and many ways to move data and synchronize between processors. The MPI+X programming model, use of which is considered by many to be standard practice, demands that a programmer be expert in both the application domain and the low-level details of the architecture(s) on which that application will be deployed, and the availability of such superhuman programmers is a critical bottleneck. Things become more complicated when evolution and change in the underlying architecture translates into significant re-engineering of the MPI+X code to maintain performance. Numerous alternatives to the MPI+X model exist, and by raising the level of abstraction on the application domain and/or the target architecture, they offer the ability for “mere mortal” programmers to take advantage of the supercomputing resources that are available to advance science and tackle urgent real-world problems.
However, compared to the MPI+X approach, these alternatives generally lack two things. First, they aren’t as well known as MPI+X and a domain scientist may simply not be aware of models that are a good fit to their domain. Second, they are less mature than MPI+X and likely have more functionality or performance “potholes” that need only be identified to be addressed. PAW-ATM is a forum for discussing HPC applications written in alternatives to MPI+X. Its goal is to bring together application experts and proponents of high-level languages to present concrete example uses of such alternatives, describing their benefits and challenges.
Topics of interest include, but are not limited to:
Submissions
Submissions are solicited in two categories:
Important Dates
Committee
Workshop Chair: Karla Vanessa Morris Wright – Sandia National Laboratories
Organizing committee
Program committee co-chairs
Call for Papers: CogArch @ ISCA 2025
https://cogarchworkshop.org
Submitted by Karthik Swaminathan
CogArch 2025 (organized by IBM Research)
Co-located with ISCA 2025
Sunday, June 22, 2025
Tokyo, Japan
The CogArch workshop emphasizes the challenges associated with the implementation of generative AI and the integration of chiplets as a means to fully realize its potential. As generative AI models continue to expand in size and complexity, the resulting computational demands impact the entire software-hardware ecosystem. This creates a variety of new challenges that necessitate unconventional strategies to maintain scalability in both upward and outward directions. With Large Language Model (LLM) parameter sizes approaching several billions, chiplet-based architectures represent a promising technological advancement that could enable a cost-effective and energy-efficient solution for processing such models, thus potentially transforming the future landscape of cognitive systems.
The CogArch workshop solicits formative ideas and new product offerings in the general space of AI systems that covers all the design aspects of cognitive systems, with particular focus this year on the adoption of chiplets as a promising way to support large-scale generative AI.
Topics of interest include (but are not limited to):
→ Accepted works will have the chance to be published in one of the leading journals in computer architecture.
Important dates:
Organizers:
Call for Papers: ARC-LG’ @ ISCA 2025
https://llm-gnn.org/
Submitted by Pavana Prakash
Workshop on New Approaches for Addressing the Computing Requirements of LLMs and GNNs (ARC-LG’) 2025
Co-located with ISCA 2025
Overview:
Training and deploying huge machine learning models, such as GPT, Llama, or large GNNs, require a vast amount of compute resources, power, storage, memory. The size of such models is growing exponentially, as is the training time and the resources required. The cost to train large foundation models has become prohibitive for everyone but very few large players. While the challenges are most visible in training, similar considerations apply to deploying and serving large foundation models for a large user base.
The proposed workshop aims to bring together AI/ML researchers, computer architects, and engineers working on a range of topics focused on training and serving large ML models. The workshop will provide a forum for presenting and exchanging new ideas and experiences in this area and to discuss and explore hardware/software techniques and tools to lower the significant barrier of entry in the computation requirements of AI foundation models.
Submissions:
Authors can submit either 8-page full papers or up to 4-page short papers. In the short paper format, out-of-the box ideas and position papers are especially encouraged.
See the website for submission details.
Topics:
The workshop will present original works in areas such as (but not inclusive to): workload characterization, inference serving at scale, distributed training, novel networking and interconnect approaches for large AI/ML workloads, addressing resilience of large training runs, data reduction techniques, better model partitioning, data formats and precision, efficient hardware and competitive accelerators.
Call for Presentations: ModSim 2025
https://www.bnl.gov/modsim/
Submitted by Jason Lowe-Power
Workshop on Modeling & Simulation of Systems and Applications (ModSim) 2025
August 13-15, 2025,
University of Washington Botanic Gardens Center for Urban Horticulture, Seattle
Workshop URL: https://www.bnl.gov/modsim/
Submission URL: https://easychair.org/conferences/?conf=modsimworkshop2025
Important Dates
EasyChair Submission Deadline: Monday, May 26, 2025 (11:59 pm PDT; 6:59 am UTC)
Notification of Acceptance: Monday, June 9, 2025 (via e-mail)
To promote advancements in modeling and simulation (ModSim) research, we are soliciting input in the form of abstracts. If accepted, author(s) will be invited to host a short presentation and/or poster at the annual gathering of our community, the Workshop on Modeling & Simulation of Systems and Applications (ModSim 2025). This year’s workshop theme is Modeling and Simulation for Extreme Computing in the AI Era. The emphasis will be on emerging and revolutionary new technologies and architectures for computing of AI workloads. ModSim for processors and system architectures design and optimization that scale and perform at the pace of AI, including novel AI-driven methodologies for ModSim, as well as tools, best practices, and new directions will be showcased and discussed throughout the workshop. As always, projects and initiatives that address computing challenges in the AI Era and aim to advance the state-of-the-art in modeling performance, power, and reliability of extreme computing will be represented. Specific areas of interest are further defined in the Topic Areas subsection of this call. Submissions related to this year’s workshop theme, imparting lessons learned from specific projects, methods, tools, and use cases, are highly encouraged. Domestic travel to ModSim 2025 may be available for full-time students at U.S.-based academic institutions, supported by a National Science Foundation travel grant.
Topic Areas:
Abstract contributions should relate to the workshop theme Modeling and Simulation for Extreme Computing in the AI Era. Within the overall theme, subcategories of interest include:
Call for Workshops/Tutorials: MICRO 2025
https://www.microarch.org/micro58/submit/workshops.php
Submitted by Alexandros Daglis, Jaewoong Sim, Yunho Oh
The International Symposium on Microarchitecture® (MICRO) is the premier forum for the presentation and discussion of new ideas in microarchitecture, compilers, hardware/software interfaces, and design of advanced computing and communication systems. The goal of MICRO is to bring together researchers in the fields of microarchitecture, compilers, and systems for technical exchange. The MICRO community has enjoyed having close interaction between academic researchers and industrial designers—we aim to continue and strengthen this longstanding tradition at the 58th MICRO in Seoul.
We invite proposals for workshops and tutorials to be held on Saturday, October 18, and Sunday, October 19, 2025, before the main symposium days.
Proposals should be one to two pages long and must include the following information:
Title of the workshop/tutorial.
Organizers and their affiliations (including short bios).
Expected duration of the workshop/tutorial; i.e., half day or full day.
If the workshop/tutorial was previously held, provide the location (i.e., which conference), date, number of published papers (if any), and number of attendees at the last event. Please also highlight what new/different content would be covered in this edition.
For a workshop proposal, provide a sample call for papers and workshop main topics.
For a tutorial proposal, provide the abstract of the tutorial.
Proposals should highlight a plan for ensuring diversity in invited speakers, tutorial presenters, and organizing and selection committees (if applicable).
Submit workshop and tutorial proposals (1–2 pages) to micro58workshops@gmail.com.
Important Dates & Information:
Submission Deadline: May 31, 2025
Notification: June 14, 2025
Workshop/Tutorial Days: October 18-19, 2025
Please view the SIGARCH website for the latest postings, to submit new posts, and for general SIGARCH information. We also encourage you to visit the Computer Architecture Today Blog.
- Akanksha Jain
SIGARCH Content Editor