This is the 1st October 2025 digest of SIGARCH Messages.
Call for Nominations: ISCA-53 Program Committee Candidate Nomination
https://iscaconf.org/isca2026/
Submitted by Carole-Jean Wu and Kevin Skadron
Dear colleagues and friends,
To provide a good experience for authors submitting their work to ISCA, and, at the same time, ensure a high-quality review experience for program committee members, in the presence of the ever-increasing submission counts and a wide range of topics of interest, we request your help.
We solicit your input to nominate qualified colleagues, especially early-career colleagues, such as recently graduated PhD students, postdoctoral researchers, or industry / government laboratory researchers who you have personally mentored and collaborated with, to serve on the ISCA program committee. We would appreciate it if you can fill out this PC nomination form by Friday, September 26 for all topic areas of interest to ISCA.
Sincerely,
Carole-Jean Wu and Kevin Skadron
ISCA-53 Program Chairs
Call for Participation: PACT 2025
https://pact2025.github.io/index
Submitted by Khaled N. Khasawneh
PACT, The International Conference on Parallel Architectures and Compilation Techniques, is a unique technical conference at the intersection of hardware and software, with a special emphasis on parallelism. PACT brings together researchers from computer architectures, compilers, execution environments, programming languages, and applications to present and discuss their latest research results, tools, and practical experiences.
Call for Papers: ISCA 2026
https://www.iscaconf.org/isca2026/submit/papers.php
Submitted by Amro Awad
The 53rd IEEE/ACM International Symposium on Computer Architecture (ISCA 2026)
June 27– July 1, 2026
Raleigh, USA
The International Symposium on Computer Architecture (ISCA) is the premier forum for new ideas and experimental results in computer architecture. The conference specifically seeks particularly forward-looking and novel submissions. As with prior ISCAs, there will be a main track and an industry track. For both tracks, the dates, topics, and some review policies are presented on ISCA’s webpage: https://www.iscaconf.org/isca2026/submit/papers.php
Topics of Interest
Papers are solicited on a broad range of topics, including (but not limited to):
– Processor, memory, and storage systems architecture
– Parallelism: instruction, thread, data, multiprocessor
– Datacenter-scale computing
– IoT, mobile, edge, and embedded architecture
– Verification, testing, and correctness
– Interconnection networks, routers, and network interface architectures
– Power and energy
– Sustainable computing
– Architectures for emerging applications including machine learning and bioinformatics
– Architectural support for programming languages or software development
– Architectural support for interfacing with accelerators
– Architectural support for security, virtual memory, and virtualization
– Dependable processor and system architecture
– Architectures for emerging technologies including novel circuits, memory technologies, etc.
– Quantum computer architecture
– Architecture modeling, simulation methodologies, and tools
– Evaluation and measurement of real computing systems
– Human factors and user studies
Important Dates:
All deadlines are 11:59 PM AoE
Main Track
Abstract Deadline November 10, 2025
Full Paper Deadline November 17, 2025
Round 1 Reviews Due December 19, 2025
Round 2 Reviews Due February 13, 2026
Rebuttal/Revision Period February 16 – March 6, 2026
Industry Track
Abstract Deadline December 5, 2025
Full Paper Deadline December 12, 2025
Round 1 Reviews Due February 6, 2026
Round 2 Reviews Due n/a
Rebuttal/Revision Period February 16 – 27, 2026 (no revisions)
Decisions Released: March 27, 2026
Organizers
General Co-Chairs: James Tuck (North Carolina State University) and Huiyang Zhou (North Carolina State University)
Program Co-Chairs: Kevin Skadron (University of Virginia) and Carole-Jean Wu (Meta)
Program Chair (Industry Track): Brad Beckmann (AMD)
Call for Papers: FCCM 2026
https://www.fccm.org/
Submitted by He Li
34th IEEE International Symposium on Field-Programmable Custom Computing Machines
May 13 – 16, 2026
Conference Site: https://www.fccm.org
LinkedIn: https://www.linkedin.com/company/fccm-conference/
The IEEE Symposium on Field-Programmable Custom Computing Machines is the original and premier forum for presenting and discussing new research related to computing that exploits the unique features and capabilities of FPGAs and other reconfigurable hardware. Over the past two decades, FCCM has been the place to present papers on architectures, tools, and programming models for field-programmable custom computing machines as well as applications that use such systems.
[New!] This year, we have launched a Reconfigurable Computing Challenge (RCC 2026)! Check out more details here: https://www.fccm.org/fccm-2026-competition/
Topics of interest:
Custom Computing and Reconfigurable Architectures:
Abstractions, Programming Models, and Tools:
Run Time Reconfiguration:
Applications:
Submission Guidelines and Processes
Research submissions can be in either of two categories:
Long — at most 8 pages (excluding references), for a regular presentation at the conference.
Short — at most 4 pages (excluding references), for a brief presentation at the conference. This category is intended for new projects and early results or work that can be concisely presented in the 4-page budget.
Submissions accepted as posters will have a one-page extended abstract.
Important Dates
All deadlines apply to the Anywhere on Earth (UTC – 12) timezone
Abstract Submission Due January 10th, 2026 (No Extensions)
Full Paper Submission Due January 17th, 2026 (No Extensions)
Rebuttal Period February 23 – 27th, 2026
Notification of Acceptance March 16th, 2026
Camera-Ready Submission Due April 4th, 2026
Questions
General question: Callie Hao (callie.hao@gatech.edu)
Program question: Lana Josipović (ljosipovic@ethz.ch)
Call for Papers: ICS 2026
https://dipsa-qub.github.io/ICS2026-webpage/
Submitted by Swaroop Pophale
40th ACM International Conference on Supercomputing (ICS 2026)
Belfast, Northern Ireland (United Kingdom)
July 6th-9th, 2026
https://dipsa-qub.github.io/ICS2026-webpage/
Important dates
ICS 2026 holds two cycles of paper submissions.
Cycle 1:
Abstract submission: December 9th, 2025
Paper submission: December 16th, 2025
Rebuttal period: Feb 10th to Feb 12th, 2026
Author notification: Feb 24th, 2026
Camera ready: March 24th, 2026
Cycle 2:
Abstract submission: February 2nd, 2026
Paper submission: February 9th, 2026
Rebuttal period: March 24th to March 26th, 2026
Author notification: April 6th, 2026
Camera ready: May 6th, 2026
Topics of Interest
Papers are solicited on all aspects of the architecture, software, and applications of high-performance computing systems of all scales (from chips to supercomputing systems), including but not limited to:
Papers will be evaluated based on their novelty, technical soundness, and potential impact on the field. The review process includes a rebuttal phase, and the committee’s discussions will take the authors’ responses into account. A paper cannot be submitted to both cycles.
Call for Papers: AccML @ HiPEAC 2026
https://accml.dcs.gla.ac.uk/
Submitted by José Cano
8th Workshop on Accelerated Machine Learning (AccML)
Co-located with HiPEAC 2026
January 27, 2026
Kraków, Poland
https://accml.dcs.gla.ac.uk/
https://www.hipeac.net/2026/krakow/#/program/sessions/8255/
Recent advances in diverse AI applications have driven the rise of heterogeneous architectures to accelerate machine learning workloads. Increasing model complexity and deployment demands have spurred the development of high-productivity systems, advanced programming abstractions, specialized runtimes, and tools. Since deep learning models are memory- and compute-intensive, acceleration reduces energy use and enables edge deployment. Beyond CNNs, newer models like Vision Transformers and LLMs introduce broader computational challenges, continually testing hardware, software stacks, and abstractions—highlighting the need for dedicated forums on ML acceleration and system design.
Topics of interest:
– Novel ML/AI systems: heterogeneous multi/many-core systems, GPUs, ASICs and FPGAs;
– Software ML/AI acceleration: languages, primitives, libraries, compilers and frameworks;
– Novel ML/AI hardware accelerators and associated software;
– Emerging semiconductor technologies with applications to ML/AI hardware acceleration;
– ML/AI for the design and tuning of hardware, compilers, and systems;
– Cloud and edge ML/AI computing: hardware and software to accelerate training and inference;
– Hardware-Software co-design techniques for more efficient model training and inference (e.g. addressing sparsity, pruning, etc);
– Training and deployment of huge LLMs (such as GPT, Llama), or large GNNs;
– Computing systems research addressing the privacy and security of ML/AI-dominated systems;
Submission
Papers will be reviewed by the workshop’s technical program committee according to criteria regarding the submission’s quality, relevance to the workshop’s topics, and, foremost, its potential to spark discussions about directions, insights, and solutions in the context of accelerating machine learning. Research papers, case studies, and position papers are all welcome.
In particular, we encourage authors to submit work-in-progress papers: To facilitate sharing of thought-provoking ideas and high-potential though preliminary research, authors are welcome to make submissions describing early-stage, in-progress, and/or exploratory work in order to elicit feedback, discover collaboration opportunities, and spark productive discussions.
The workshop does not have formal proceedings.
Important Dates
Submission deadline: November 21, 2025
Notification of decision: December 5, 2025
Organizers
José Cano (University of Glasgow)
Valentin Radu (University of Sheffield)
José L. Abellán (University of Murcia)
Marco Corner (Google DeepMind)
Ulysse Beaugnon (Google DeepMind)
Juliana Franco (Google DeepMind)
Call for Presentations: CACHP @ PPoPP 2026
https://fastcode.org/events/coevolution-workshop/
Submitted by Bruce Hoppe
Workshop on Co-evolution of Algorithms, Compilers, and Hardware for Performance (CACHP)
Co-located with PPoPP 2026
31 January – 4 February 2026
Sydney, Australia
Achieving performance requires advances in various aspects, including algorithms, programming models, software construction, compilers, and hardware. Progress in each of these areas influences and reshapes the others. For example, a new code pattern may first appear as a hand-crafted optimization by an expert programmer, then evolve into a portable compiler transformation, and eventually inspire changes in hardware architecture or system design. Such cross-pollination drives innovation, yet opportunities for the communities to engage in joint discussion remain limited.
The workshop will be organized as a half-day event (approximately four hours). We are soliciting talk proposals to introduce recent advances as well as challenges that could shape the next generation of research. Importantly, the workshop emphasizes idea exchange rather than publication, so it does not require proceedings.
Paper Submission
All submissions must be made electronically through EasyChair (https://easychair.org/conferences/?conf=cachp26). A submission should include the abstract and a high-level description of the work covered by the proposed talk. Each talk is around 20 minutes. All submissions must include a title, an abstract, and a description of the talk, and should be no longer than one page. Authors can provide additional links to related publications. A talk can feature one or multiple publications (e.g., a series of related ones). We especially encourage work that covers novel designs of algorithms, compilers, or hardware inspired by one another. Submissions will be peer-reviewed, and accepted submissions will be invited to give talks at the workshop.
We do not have a strict format requirement since the workshop does not require proceedings. Using the ACM SIGPLAN template is recommended.
Important Dates:
Organizing Team:
For any questions, please don’t hesitate to contact any of the organizers.
Call for Presentations: Arch4Health @ MICRO 2025
https://events.safari.ethz.ch/micro25-arch4health/
Submitted by Nika Mansouri Ghiasi
1st Workshop on Architecture for Health (Arch4Health 2025)
In conjunction MICRO 2025
18th October 2025, Seoul, Korea
A half-day workshop exploring the key computational challenges in health-related applications and the vital role of computer architecture in overcoming them to advance healthcare
Summary:
Opportunities. Recent biotechnological advances enable high-throughput, low-cost, and accurate biological data generation (e.g., using genome sequencing, multimodal medical imaging, continuous wearable sensing). This wealth of data enables unique opportunities for advancing healthcare.
Challenges. Despite these opportunities, efficiently analyzing large-scale biological data poses significant challenges for conventional computing systems. These systems often cannot keep up with the high-throughput rate at which data is generated, and they face additional constraints related to energy efficiency, scalability, privacy, and security. High-throughput processing is especially critical in clinical settings, where faster analysis can improve patient outcomes. Therefore, there is a need to design systems to enable high-performance, energy-efficient, private, and secure analysis of biological data.
Architecture for Health. This workshop will focus on identifying key computational challenges in health-related applications and discussing how computer architects can contribute to advancing healthcare by addressing these challenges.
Fostering Diverse and Cross-Disciplinary Discussions. Since cross-disciplinary discussions are crucial for better identifying challenges in real-world health-related applications, we aim to foster open discussions and cooperation between researchers with diverse backgrounds (i.e., from both computer architecture and health sciences communities, industry, and academia).
Call for Presentations:
This workshop consists of talks on the general topic of computing system designs for healthcare applications and new trends and bottlenecks in data-intensive healthcare applications. There are a limited number of slots for talks. If you are interested in delivering a talk on related topics,
please submit your talk’s title and extended abstract via this form: https://forms.gle/ozKpsox1LT2vt9aP7
Further submission information: https://events.safari.ethz.ch/micro25-arch4health/
Topics of Interest
We invite abstract submissions related to (but not limited to) the following topics:
Important Dates
Organizers:
Nika Mansouri Ghiasi, ETH Zurich
Konstantina Koliogeorgi, ETH Zurich
Onur Mutlu, ETH Zurich
Call for Workshops/Tutorials: EuroSys 2026
https://forms.gle/NnVuzMFsKFTpvJ3Z9
Submitted by Christina Giannoula
Submit your workshop & tutorial proposals for EuroSys2026
Topics include OS, distributed systems, security, AI/ML & more.
Deadline: Oct 31, 2025. Apply via: https://forms.gle/NnVuzMFsKFTpvJ3Z9
Call for Workshops/Tutorials: General Purpose Processing using GPU (GPGPU) @ PPoPP 2025
https://mocalabucm.github.io/gpgpu2025/
Submitted by Daniel Wong
The 17th Workshop on General Purpose Processing using GPU (GPGPU) 2025
Held in cooperation with PPoPP 2025
Half-Day Workshop (March 1 or 2, 2025)
Las Vegas, NV, USA
https://mocalabucm.github.io/gpgpu2025/
Overview
GPUs are delivering more and more computing power required by modern society. With the growing popularity of massively parallel devices, users demand better performance, programmability, reliability, and security. The goal of this workshop is to provide a forum to discuss massively parallel applications, environments, platforms, and architectures, as well as infrastructures that facilitate related research.
Topics of interest
Authors are invited to submit papers of original research in the general area of GPU computing and architectures. Topics include, but are not limited to:
– GPU Architecture and Hardware
– Next-generation GPU architectures
– Energy-efficient GPU designs
– Scalable multi-GPU systems
– GPU memory hierarchies and management
– Programming Models and Compilers
– High-level programming abstractions for GPUs
– Compiler optimizations for GPU codes
– Source-to-source translations and tools
– Debugging and profiling tools for GPUs
– GPU Algorithms and Data Structures
– Parallel algorithms tailored for GPUs
– Data structures optimized for GPU memory hierarchies
– Algorithmic primitives and building blocks
– Performance Optimization Techniques
– Performance modeling and benchmarking
– Auto-tuning and performance portability
– Techniques for reducing communication overheads
– GPU Applications
– Case studies of real-world GPU applications
– GPU applications in scientific computing, machine learning, large language models, graphics, and emerging field (e.g., quantum, neuromorphic, bioinformatics and genomics)
– Performance comparisons between GPU and other parallel computing platforms
– Integration of GPUs with Other Technologies
– GPU and FPGA co-processing
– Hybrid systems (e.g., CPU-GPU, GPU-TPU integration)
– Cloud-based GPU computing
– Challenges and Future Trends
– Reliability and fault tolerance in GPU systems
– Security and privacy concerns in GPU computing
– The future of heterogeneity in computing platforms
– GPU programming and architecture education
Deadlines
Important Dates (Tentative) (11:59 pm, Anywhere on Earth)
Papers due: December 2, 2024 December 16, 2024 (Extended Deadline)
Notification: January 20, 2025
Final paper due: February 17, 2025
Submission Guidelines
Full paper submissions must be in PDF format for A4 or US letter-size
paper. They must not exceed 6 pages (excluding references) in standard
ACM two-column sigplan format (review mode, sigplan template). Authors
can select if they want to reveal their identity in the submission.
Templates for ACM format are available for Microsoft Word, and LaTeX
at: https://www.acm.org/publications/proceedings-template.
Call for Workshops/Tutorials: Call for Workshops/Tutorials @ HPCA 2026
https://hpca-conf.org/2026/workshop-tutorial-cfp/
Submitted by Tom St. John
32nd IEEE International Symposium on High-Performance Computer Architecture (HPCA) seeks proposals for workshops and tutorials.
Workshops and tutorials will be held on Saturday (January 31, 2026) and Sunday (February 1, 2026) before the main conference.
HPCA will be held in-person in Sydney, Australia.
Important Dates
Proposal submission deadline: October 3, 2025
Notification: October 17, 2025
Proposal Format
Proposals should be one to two pages, and must include at least the following information:
Proposals should highlight a plan for ensuring diversity in invited speakers, tutorial presenters, and organizing and selection committees (if applicable).
Proposals (in PDF format) should be sent via email to wt.hpca2026@gmail.com
Call for Workshops/Tutorials: ASPLOS 2026
https://www.asplos-conference.org/call-for-workshops-and-tutorials/
Submitted by Hyeran Jeon & ,
We solicit workshop and tutorial proposals for ASPLOS 2026 in Pittsburgh, PA. Workshops and tutorials will be held on March 22 (Sunday) and March 23 (Monday) 2026.
Workshops
We encourage proposals in the interplay between programming languages, computer architecture, systems, and user interfaces to deal with challenges such as power, performance, resilience, and programmer productivity in emerging areas including but not limited to datacenter/cloud computing, systems based on non-volatile memory technologies, large-scale data analysis, smart infrastructure, extreme-scale computing, systems for AI/ML, system security, and large language model (LLM) applications.
Tutorials
We solicit proposals for both half and full-day tutorials on any topic that is relevant to the ASPLOS audience. In previous years, tutorials seeking to achieve either of the following goals have been particularly successful:
Important Dates
Workshops & Tutorials Submission Deadline: November 3rd, 2025 (Monday)
Notification: November 21st, 2025 (Friday)
Submission
The submission site is coming soon!
Feel free to reach out to ASPLOS 2026 workshop/tutorial chairs Adwait Jog and Ashutosh Pattnaik at wt.asplos2026@gmail.com
Episode 21 of the Computer Architecture Podcast Released! Featuring Guest Dr. Caroline Trippel, Stanford University
https://comparchpodcast.podbean.com/
Submitted by Suvinay Subramanian
Computer Architecture Podcast: A series of conversations on cutting-edge work in computer architecture and the remarkable people behind it.
Announcing the release of Episode 21: High-assurance Computer Architectures with Dr. Caroline Trippel, who is an Assistant Professor in the Computer Science and Electrical Engineering Departments at Stanford University. Caroline’s research operates at the critical intersection of hardware and software, focusing on developing high-assurance computer architectures. Her work tackles the challenge of ensuring that complex hardware designs are correct and secure. She has pioneered automated tools that bridge the gap between a processor’s implementation (its RTL) and its formal specification, as well as frameworks and compilers that find and mitigate hardware-related security vulnerabilities in software.
Listen to the episode at https://comparchpodcast.podbean.com. Also available on your favorite podcast player — iTunes, Spotify, Stitcher, etc.
Please view the SIGARCH website for the latest postings, to submit new posts, and for general SIGARCH information. We also encourage you to visit the Computer Architecture Today Blog.
- Akanksha Jain
SIGARCH Content Editor