Call for Papers: ARCS 2026: Open-Source Architectures: From RISC-V to AI Accelerators
https://arcs-conference.org/
Submitted by Mathias Pacher

39th GI/ITG International Conference on Architecture of Computing Systems (ARCS 2026)

The ARCS conferences series has over 38 years of tradition on reporting leading-edge research in computer architecture and operating systems. New chips are designed either as general-purpose devices with a wide user portfolio in mind, or target the needs of specific applications (e.g. machine learning pipelines for deep learning workloads, mobile or embedded systems). Accordingly, they might rely on well-established architectural approaches
(CPU-like, vector extensions), or bring completely new disruptive ideas limiting energy consumption. In this landscape, ARCS stands out in hosting and presenting such concepts and ideas for versatile architectures. Nowadays, such architectures often include open-source solutions such as RISC-V or AI accelerators, which are drawing more and more attention in academia and industry. ARCS’26 aims to leverage this growing interest in such architectures to foster their development, performance, and dissemination. We welcome all contributions on hardware architectures, as well as their programming models, software stacks (operating systems, compilers…), their insertion into computing systems, and the challenges to port optimized code.

In addition to the main conference, ARCS will host:
-A special track on Organic Computing.
-A special track on Dependability and Fault Tolerance.
-A PhD forum to present the work of young doctoral students (10 page papers).
-A Group forum for new professors, individual researchers, and consortia to present their research (5 page papers).

The proceedings of ARCS 2026 will be published in the Springer Lecture Notes on Computer Science (LNCS) series. A best paper will be elected by the Program Committee, and the Participants’ Favourite Presentation Award will be chosen by the audience.

Topics of Interest
Paper submission: Authors are invited to submit original,
unpublished research papers on one or more of the following topics:

Hardware Architectures
* Reconfigurable architectures
* System-on-chip
* Parallel and distributed systems
* High performance systems
* Heterogeneous many-core architectures
* Domain-specific accelerator architectures
* Real-time and mixed-criticality systems
* I/O and non-volatile memory
* Energy-efficient architectures
* Smart network technologies
* RISC-V and open-source architectures
* AI accelerators
* Dependable and fault-tolerant architectures

Programming Models and Runtime Environments
* Programming models for heterogeneous computing
* Tools for power monitoring and performance analysis
* Operating systems, algorithms, and data structures for heterogeneous architectures
* Hypervisors and middleware for homogeneous and heterogeneous multi-/many-core computing platforms
* System management including but not limited to scheduling, memory management, power/thermal management, and RTOS
* Domain-specific languages and programming models
* Architecture-specific code generation and optimization
* Architectural simulation and emulation

Cross-sectional Topics
* Near-memory and in-memory computing
* Memory and network compression technologies
* Organic Computing
* Pervasive systems
* Autonomous systems
* Approximate Computing
* Mixed-criticality systems
* Support for safety and security
* Hardware in the loop
* Optimization and performance analysis

Call for Papers: CP 2026: ACM International Conference on Computing Frontiers
https://www.computingfrontiers.org/2026/index.html
Submitted by Dipika Deb

23rd ACM International Conference on Computing Frontiers (CF 2026)
May 19-21, 2026
Catania, Sicily, Italy

Computing Frontiers (CF) is an eclectic, interdisciplinary, collaborative community of researchers investigating emerging technologies in the broad field of computing: our common goal is to drive the scientific breakthroughs that support society.

We seek original research contributions at the frontiers of a wide range of topics, including novel computational models and algorithms, new application paradigms, computer architecture (from embedded to HPC systems), computing hardware, memory technologies, networks, storage solutions, compilers, and runtime environments. 

Topics of Interest

• Hardware Frontiers
  Emerging processor architectures, accelerators and memory systems
  Post-exascale high-performance computing
  Quantum computing systems, runtimes, algorithms and applications
  Post-Moore’s Law Systems: Neuromorphic, biologically-inspired, superconducting, and hyperdimensional computing 
• Distributed Systems and Networking Frontiers
  Multi and Hybrid Cloud computing, and challenges
  IoT, CPS, edge and embedded computing systems
  Breakthroughs in edge-cloud continuum, satellite computing
  Sensor networks and wearable computing
• System Software and Runtime Frontiers
  Virtualization and containerization
  Platforms for workflows and distributed programming
  Compilers and optimizations for heterogeneous systems
  Big data platforms and analytics
• AI for Systems and Systems for AI
  Distributed AI and federated learning
  System design for efficient AI
  AI for system optimizations
  Agentic AI and AIOps 
• Cutting-edge Developments in Computing for Society and Emerging Applications
  AI ethics: Privacy, sustainability, biases
  Emerging applications in education, health, smart cities and emerging markets 
• Pushing the Boundaries of Cross-cutting Computing Challenges
  Designing for scale and performance
  Energy efficiency and sustainability
  Security and privacy, impact of quantum and AI
  Reliability, resiliency and dependability
  Algorithmic innovations
  Benchmarking, performance analysis and modeling

We strongly encourage submissions in other emerging fields of computing, and welcome submissions that propose new directions of research and out-of-the-box solutions for grand computing challenges. If you are in doubt whether your work fits Computing Frontiers, please contact the program co-chairs.

Important Dates
Abstract submission deadline: January 12, 2026
Paper submission deadline: January 19, 2026
Author notification: March 9, 2026
Camera-ready version due: April 6, 2026

Organizers
Chairs:
Hubertus Franke, IBM Research, US
Maurizio Palesi, University of Catania, IT

Call for Papers: ISPASS 2026
https://ispass.org/ispass2026/
Submitted by Udit Gupta

IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2026)
April 26-28, 2026
Seoul, South Korea

Topics of Interest

• Performance and efficiency (power, area, etc.) evaluation methodologies
  • Analytical modeling
  • Statistical approaches
  • Tracing and profiling tools
  • Simulation techniques
  • Hardware (e.g., FPGA) accelerated simulation
  • Hardware performance counter architectures
  • Power, temperature, variability and/or reliability models for computer systems
  • Microbenchmark-based hardware analysis techniques
• Foundations of performance and efficiency analysis
  • Metrics
  • Bottleneck identification and analysis
  • Visualization
• Efficiency and performance analysis of commercial and experimental hardware
  • Multi-threaded, multicore and many-core architectures
  • Accelerators and graphics processing units
  • Memory systems, including storage-class memory
  • Embedded and mobile systems
  • Enterprise systems and data centers
  • HPC and Supercomputers
  • Computer networks
  • Quantum computing
  • Emerging technologies
• Efficiency and performance analysis of emerging workloads and software
  • Software written in managed languages
  • Virtualization and consolidation workloads
  • Datacenter, internet-sector workloads
  • Embedded, multimedia, games, telepresence
  • Deep learning and convolutional neural networks
• Application and system code tuning and optimization
• Confirmations or refutations of important prior results

In addition to research papers, ISPASS welcomes tool and benchmark paper submissions. The conference is an ideal forum to introduce new tools and benchmarks to the community. These papers, which can detail tools and benchmarks in the above fields of interest, will be judged primarily on their potential to enable and amplify future research, which should be clearly motivated in the paper. We expect authors of accepted tools/benchmark papers to open-source their tool/benchmark before the conference.

Important Dates

• Paper abstract submission deadline: December 5 2025, 11:59:59 PM, Anywhere on Earth
• Full submission deadline: December 12, 2025, 11:59:59 PM, Anywhere on Earth
• Rebuttal: February 2-5, 2026
• Paper notification: February 23, 2026

Organizers
John Kim (General Chair <jjk12@kaist.edu>)
Brandon Reagen (Program Chair <bjr5@nyu.edu>) 

Call for Papers: ISCA 2026
https://www.iscaconf.org/isca2026/submit/papers.php
Submitted by Amro Awad

The 53rd IEEE/ACM International Symposium on Computer Architecture (ISCA 2026)
June 27– July 1, 2026
Raleigh, USA

The International Symposium on Computer Architecture (ISCA) is the premier forum for new ideas and experimental results in computer architecture. The conference specifically seeks particularly forward-looking and novel submissions.  As with prior ISCAs, there will be a main track and an industry track. For both tracks, the dates, topics, and some review policies are presented on ISCA’s webpage: https://www.iscaconf.org/isca2026/submit/papers.php

Topics of Interest
Papers are solicited on a broad range of topics, including (but not limited to):

– Processor, memory, and storage systems architecture
– Parallelism: instruction, thread, data, multiprocessor
– Datacenter-scale computing
– IoT, mobile, edge, and embedded architecture
– Verification, testing, and correctness
– Interconnection networks, routers, and network interface architectures
– Power and energy
– Sustainable computing
– Architectures for emerging applications including machine learning and bioinformatics
– Architectural support for programming languages or software development
– Architectural support for interfacing with accelerators
– Architectural support for security, virtual memory, and virtualization
– Dependable processor and system architecture
– Architectures for emerging technologies including novel circuits, memory technologies, etc.
– Quantum computer architecture
– Architecture modeling, simulation methodologies, and tools
– Evaluation and measurement of real computing systems
– Human factors and user studies

Important Dates:
All deadlines are 11:59 PM AoE

Main Track
Abstract Deadline November 10, 2025
Full Paper Deadline November 17, 2025
Round 1 Reviews Due December 19, 2025
Round 2 Reviews Due February 13, 2026
Rebuttal/Revision Period February 16 – March 6, 2026

Industry Track
Abstract Deadline December 5, 2025
Full Paper Deadline December 12, 2025
Round 1 Reviews Due February 6, 2026
Round 2 Reviews Due n/a
Rebuttal/Revision Period February 16 – 27, 2026 (no revisions)

Decisions Released: March 27, 2026

Organizers
General Co-Chairs: James Tuck (North Carolina State University) and Huiyang Zhou (North Carolina State University)
Program Co-Chairs: Kevin Skadron (University of Virginia) and Carole-Jean Wu (Meta)
Program Chair (Industry Track): Brad Beckmann (AMD)

Call for Papers: FCCM 2026
https://www.fccm.org/
Submitted by He Li

34th IEEE International Symposium on Field-Programmable Custom Computing Machines
May 13 – 16, 2026
Conference Site: https://www.fccm.org
LinkedIn: https://www.linkedin.com/company/fccm-conference/

The IEEE Symposium on Field-Programmable Custom Computing Machines is the original and premier forum for presenting and discussing new research related to computing that exploits the unique features and capabilities of FPGAs and other reconfigurable hardware. Over the past two decades, FCCM has been the place to present papers on architectures, tools, and programming models for field-programmable custom computing machines as well as applications that use such systems.
[New!] This year, we have launched a Reconfigurable Computing Challenge (RCC 2026)! Check out more details here: https://www.fccm.org/fccm-2026-competition/

Topics of interest:
Custom Computing and Reconfigurable Architectures:

• Heterogeneous and mixed signal digital/analog field customizable accelerators
• Neuromorphic emulation and accelerators
• Memory centric computing architectures
• Overlays, coarse grained reconfigurable architectures
• Clusters, data centers, and large systems IoT and Embedded SoC, MPSoC architectures
• Security enhancements for reconfigurable computing
• Customizable soft processor systems

Abstractions, Programming Models, and Tools:

• Use of Large Language Models (LLMs) for FPGA design
• Domain-specific languages, frameworks, and open-source hw/sw synthesis/compilation tools
• Software-defined-systems (e.g. radio, networks, frameworks for new domains)
• CAD tools, abstractions, and languages for mixed analog/digital fabrics

Run Time Reconfiguration:

• Run-time management and scheduling of reconfigurable hardware
• System resilience/fault tolerance for reconfigurable hardware
• Evolvable, adaptable, approximate, or autonomous reconfigurable computing systems
• Security assessment and enhancement of run-time reconfiguration

Applications:

• Evaluations and analysis on custom computing architectures with GPUs, NPUs, or DSPs
• Post Quantum Cryptography, Quantum control and emulation

Submission Guidelines and Processes
 Research submissions can be in either of two categories:
Long — at most 8 pages (excluding references), for a regular presentation at the conference.
Short — at most 4 pages (excluding references), for a brief presentation at the conference. This category is intended for new projects and early results or work that can be concisely presented in the 4-page budget.

Submissions accepted as posters will have a one-page extended abstract.

Important Dates
 All deadlines apply to the Anywhere on Earth (UTC – 12) timezone
Abstract Submission Due               January 10th, 2026 (No Extensions)
Full Paper Submission Due            January 17th, 2026 (No Extensions)
Rebuttal Period                               February 23 – 27th, 2026
Notification of Acceptance              March 16th, 2026
Camera-Ready Submission Due    April 4th, 2026

Questions
General question: Callie Hao (callie.hao@gatech.edu)
Program question: Lana Josipović (ljosipovic@ethz.ch)

Call for Papers: ICS 2026
https://dipsa-qub.github.io/ICS2026-webpage/
Submitted by Swaroop Pophale

40th ACM International Conference on Supercomputing (ICS 2026)
Belfast, Northern Ireland (United Kingdom)
July 6th-9th, 2026
https://dipsa-qub.github.io/ICS2026-webpage/

Important dates
ICS 2026 holds two cycles of paper submissions.

Cycle 1:
Abstract submission: December 9th, 2025
Paper submission: December 16th, 2025
Rebuttal period: Feb 10th to Feb 12th, 2026
Author notification: Feb 24th, 2026
Camera ready: March 24th, 2026

Cycle 2:
Abstract submission: February 2nd, 2026
Paper submission: February 9th, 2026
Rebuttal period: March 24th to March 26th, 2026
Author notification: April 6th, 2026
Camera ready: May 6th, 2026

Topics of Interest

Papers are solicited on all aspects of the architecture, software, and applications of high-performance computing systems of all scales (from chips to supercomputing systems), including but not limited to:

• Processor, accelerator, memory, storage, interconnect, and system architectures, including architectures based on future and emerging hardware (e.g. quantum, superconducting, photonic, neuromorphic).
• Programming languages, paradigms, and execution models, including domain-specific languages and scientific problem-solving software environments.
• Compilers, runtime systems and system software, including optimization and support for hardware resources and energy management.
• High-performance algorithms and applications including machine learning and large-scale data analytics, as well as the implementation and deployment of algorithms and applications on large-scale systems.
• Tools for measurement, modeling, analysis, and visualization of performance, energy, or other quantitative properties of high-performance computing systems.

Papers will be evaluated based on their novelty, technical soundness, and potential impact on the field. The review process includes a rebuttal phase, and the committee’s discussions will take the authors’ responses into account. A paper cannot be submitted to both cycles.

Call for Papers: ACM Sigmetrics 2026: Operational Systems Track
https://www.sigmetrics.org/sigmetrics2026/
Submitted by Stefan Schmid (TU Berlin)

ACM Sigmetrics would like to point the community to a new track which may be of interest to some of you.

Operational Systems Track at ACM Sigmetrics 2026: This is a new track that seeks papers describing deployed systems that are in significant use in a real-world setting.

Papers in this track should focus on principled measurement, modeling, and metrics pertaining to the system. Papers in this track need not necessarily present new ideas as judged by the “academic novelty” standard that we traditionally use for research paper submissions.
Good papers could present how known ideas work in practice, how design principles scale (or do not scale) to large production-scale systems, prove (or, disprove) existing assumptions with real-world data, bring out new performance modeling problems from real-world systems to the attention of the research community, etc.
The paper must describe “lessons learned” in the context of prior approaches known in the literature. Accepted papers in this track will be published as a regular paper along with papers in the research track.

More information at https://www.sigmetrics.org/sigmetrics2026/

Call for Papers: ASPLOS 2026
https://www.asplos-conference.org/asplos2026/cfp/
Submitted by Hyeran Jeon & Guangyu Sun

ASPLOS, the ACM International Conference on Architectural Support for Programming Languages and Operating Systems, is the premier academic forum for multidisciplinary applied computer systems research spanning hardware, software, and their interaction. It focuses on practical aspects of computer architecture, programming languages, operating systems, and associated areas such as networking and storage.

Please note the following main changes from previous years detailed in the rest of the CFP

1. Two submission cycles
2. Limit on the number of submissions by the same author
3. Explicit assessment of Interdisciplinary research
4. Unlimited appendix

https://www.asplos-conference.org/asplos2026/cfp/

Important Dates

ASPLOS 2026 has moved to two submission deadlines – spring and summer – which are meant to encourage authors to submit their papers when they are ready. As in recent years, ASPLOS 2026 will allow the authors of some submissions to choose to apply a major revision to their submission in order to fix a well-defined list of problems.

Spring Cycle

• Abstract submission — March 05, 2025 (11:59pm Eastern)
• Full paper submission — March 12, 2025
• Author response — June 09 — 13, 2025
• Notification — June 24, 2025

Summer Cycle

• Abstract submission — Aug 13, 2025 (11:59pm Eastern)
• Full paper submission — Aug 20, 2025
• Author response — Nov 10 — 14, 2025
• Notification — Nov 24, 2025

Scope and Expectations

The scope of ASPLOS 2026 covers all practical aspects related to the three main ASPLOS disciplines: computer architecture, programming languages, and operating systems, as well as closely-related associated areas. ASPLOS construes systems broadly, and areas of interest include, but are not limited to: operating systems, file and storage systems, distributed systems, cloud computing, mobile and edge systems, secure and reliable systems, systems aspects of big data and machine learning, embedded and real-time systems, and virtualization.

We seek original, high-quality research submissions that improve and further the knowledge of applied computer systems, with emphasis on the intersection between the main ASPLOS disciplines:  Operating Systems, Programming Languages, Computer Architecture and Emerging Hardware.

Research submission may be applicable to computer systems of any scale, ranging from small, ultra-low power wearable devices to large scale parallel computers and data centers. We embrace research that directly targets new problems in innovative ways. The research may target diverse goals, such as throughput, latency, energy, and security. Non-traditional topics are encouraged, and the review process will be sensitive to the challenges of multidisciplinary work in emerging areas. We welcome submission of “experience papers” that have a novel component and that clearly articulate the lessons learned. We likewise welcome submissions whereby novelty lies in furthering our understandings of existing systems, e.g., by uncovering previously unknown, valuable insights or by convincingly refuting prior published results and common wisdom. We value submissions more highly if they are accompanied by clearly defined artifacts not previously available, including traces, original data, source code, or tools developed as part of the submitted work. We particularly encourage new ideas and approaches.

Alphabetically sorted areas of interest related to practical aspects of computer architecture, programming languages, and operating systems include but are not limited to:

• Existing, emerging, and nontraditional compute platforms at all scales
• Heterogeneous architectures and accelerators
• Internet services, cloud computing, and datacenters
• Memory, storage, networking, and I/O
• Power, energy, and thermal management
• Profiling, debugging, and testing
• Security, reliability, and availability
• Systems for enabling parallelism and computation on big data
• Virtualization and virtualized systems

A good submission will typically: motivate a significant problem; propose a practical solution or approach that makes sense; demonstrate not just the pros but also the cons of the proposal using sound experimental methods; explicitly disclose what has and has not been implemented; articulate the new contributions beyond previous work; and refrain from overclaiming, focusing the abstract and introduction sections primarily on the difference between the new proposal and what is already available. The latter statement should be interpreted broadly to also encompass studies that broaden our understanding of existing systems (rather than suggest new ones), which may constitute a significant problem in its own right. Submissions will be judged on relevance, novelty, technical merit, clarity. Submissions are expected to adhere to SIGPLAN’s Empirical Evaluation Guidelines and all the policies specified below.

Program Chairs

Benjamin C. Lee, University of Pennsylvania
Harry Xu, University of California Los Angeles
Mark Silberstein, Technion – Israel Institute of Technology

Please direct any questions to the program co-chairs at asplos2026pcchairs@gmail.com.

Call for Papers: PPoPP 2026
https://ppopp26.sigplan.org/
Submitted by Kenjiro Taura

31st ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming (PPoPP 2026)
Sydney, Australia
Co-located with CC, CGO and HPCA
January 31 – February 4, 2026.
https://ppopp26.sigplan.org/

Important dates:
* Full paper submission: Monday, September 1st, 2025
* Author response period: October 27 – 29, 2025 (Mon – Wed)
* Author notification: Monday, November 10th, 2025
* Artifact submission to AE committee: Monday, November 17th, 2025
* Artifact notification by AE committee: Monday, January 5th, 2026
* Final paper due: Friday, January 9, 2026 (TBC)

Scope:
PPoPP is the premier forum for leading work on all aspects of parallel and performance programming, including theoretical foundations, techniques, languages, compilers, runtime systems, tools, applications, and practical experience. This symposium focuses on improving the programming productivity and performance engineering of all concurrent and parallel systems – multicore, multi-threaded, heterogeneous, clustered, and distributed systems, grids, accelerators such as ASICs, GPUs, FPGAs, data centers, clouds, large scale machines, and quantum computers. PPoPP is also interested in new and emerging parallel workloads and applications, such as artificial intelligence and large-scale scientific/enterprise workloads.

Specific topics of interest include (but are not limited to):
* Languages, compilers, and runtime systems for parallel programs
* Parallel programming frameworks and domain-specific languages
* Parallel programming for emerging hardware, including AI accelerators, processor-in-memory, programmable logic, and non-volatile memory technologies
* High-performance libraries
* Parallel programming for deep memory hierarchies including nonvolatile memory
* Parallel algorithms
* Parallel applications including scientific computing and enterprise workloads
* Artificial intelligence and machine learning for parallel systems, including their use in system design, optimization, and runtime decisions
* Development, analysis, or management tools
* Performance analysis, debugging and optimization
* Productivity tools for parallel systems
* Software engineering for parallel programs
* Parallel programming theory and models
* Formal analysis and verification
* Concurrent data structures
* Synchronization and concurrency control
* Fault tolerance for parallel systems
* Middleware for parallel systems

Paper Submission:
Submission URL: https://ppopp26.hotcrp.com

All submissions must be made electronically through the conference website and include an abstract (100–400 words), author contact information, the full list of authors and their affiliations. Full paper submissions must be in PDF format printable on both A4 and US letter-size paper. All papers must be prepared in two-column ACM Conference Format

Further details available at https://ppopp26.sigplan.org/track/PPoPP-2026-papers#Call-for-Papers

PC co-chairs:
Madan Musuvathi (Microsoft Research)
Kenjiro Taura (The University of Tokyo)

Call for Papers: IEEE Cross-Disciplinary Conference on Memory-Centric Computing
https://ccmcc.eclectx.org/cfp.html
Submitted by Saugata Ghose

IEEE Cross-disciplinary Conference on Memory-Centric Computing (CCMCC)
Dresden, Germany
October 8–10, 2025
https://ccmcc.eclectx.org/cfp.html

The IEEE Cross-disciplinary Conference on Memory-Centric Computing (CCMCC) is a new conference that aims to bring experts from diverse fields together, all working on advancing memory-centric computing, including processing in memory and processing near memory. It is a platform for sharing new ideas, exchanging insights, and fostering collaboration. CCMCC’s mission is to accelerate innovation in memory-centric computing and its the integration into real-world applications.

We are soliciting papers across the entire memory-centric computing stack, from software to architecture to circuits and devices. You can see a broader list of topics on the CFP.

Abstracts are due June 2, with full drafts due on June 9.
Papers are due June 15th. We are accepting both long (10-12 page) and short (4-6) page papers. Please consider submitting!

Call for Papers: MEMOCODE 2025
https://memocode2025.github.io/
Submitted by Geovani Benita

MEMCODE 2025 – 23rd ACM/IEEE International Symposium on Formal Methods and Models for System Design (FMCPS)
Part of ESWEEK 2025
October 02-03, 2025, TAIPEI, TAIWAN

MEMOCODE, originally a forum on methods and models for hardware-software codesign, has become a privileged forum to discuss on formal methods and models for the design of cyber-physical system and the verification of its safety and security requirements (FMCPS).

MEMOCODE’25 is a part of ESWEEK 2025, which will take place in Taipei, Taiwan. Registered attendees can attend sessions in any of the online events, including the conferences (CASES, CODES+ISSS, EMSOFT), symposia, tutorials, workshops, and education classes.

https://memocode2025.github.io/
https://esweek.org/memocode/

Selected accepted papers will be invited to extend their accepted papers for a special edition in a journal such as the ACM Transactions on Embedded Computing Systems (ACM TECS). See more on this at the end of this CFP.

Topics of interest
MEMOCODE solicits research papers on formal methods in system design that address the foundations, engineering methods, tools, or experimental case studies. Research areas of interest include, but are not limited to, the following:

• Modeling Languages, Methods, and Tools
• Formal Methods and Tools
• Models and Methods for Developing Critical Systems
• Quantitative/Qualitative Reasoning
• Formal Methods/Models in Practice
• AI/LLM Assisted Formal Verification/testing

Important Dates
Abstract submission deadline: April 28, 2025; May 8, 2025;  May 23, 2025 (FINAL)
Paper submission deadline: May 5, 2025; May 23, 2025 (FINAL)
Notification of acceptance: Jul 8, 2025
 Final version of papers: August 11, 2025

Submissions
MEMOCODE’25 calls for three kinds of submissions: regular papers, late-breaking results, and tool presentations. All papers must be written in English and formatted according to the ACM Sigconf style conference template. A double-blind review process will be enforced. Authors must not reveal their identity directly or indirectly. Submission of papers is handled via HotCRP.

• Regular papers are no longer than ten (10) pages, excluding bibliography and appendices. They should describe original work that does not overlap with another publication or a submission under review or accepted for publication by any other conference or journal. Reviewers will check regular papers for the soundness and novelty of the proposed solutions.
• Tool papers are no longer than eight (8) pages, excluding bibliography and appendices. They should describe an existing and publicly available tool that implements relevant methods. The methods might have been published before, but the tool should not have been described in a tool paper previously. In addition to reviewing the paper, reviewers will assess the tool itself using inputs and a user’s manual provided by the authors on the tool’s web page.
• Late-breaking Results (LB) papers are no longer than four (4) pages, excluding bibliography and appendices. They should describe a promising and novel idea with a potential to get breakthrough in the field. Reviewers will judge the novelty of the idea, but do not yet expect proofs for the envisioned results.

For questions regarding technical submissions, feel free to contact one of the program committee co-chairs. All accepted papers (regular papers, late-breaking results, and tool papers) will be submitted for inclusion in ACM Digital Library. Publication in the proceedings is contingent on one author registering for and presenting the paper at the conference.

Outstanding Paper Award
A selection of papers will be recognized as outstanding papers and will be highlighted on the symposium website.

Special Edition for Journal
Selected accepted papers will be invited to extend their accepted papers (at least 30% extension over the accepted version) for a special edition in a journal such as the ACM Transactions on Embedded Computing Systems (ACM TECS) or Leibniz Transactions on Embedded Systems (LITES). Kindly follow the call for submissions for the special edition to check the relevant deadlines and timeline of the review process. Note that the extended version of the paper will go through a separate review process in the journal.

Organizing committee
General Chairs: 
Claire Pagetti, ONERA, France
Nan Guan, City University of Hong Kong

Program Chairs:
Srinivas Pinisetty, Indian Institute of Technology Bhubaneswar, India
Sudipta Chattopadhyay, Singapore University of Technology and Design

Keynote Speakers:
Sanjay Lall, Stanford University
Naijun Zhan, Peking University

Call for Papers: IEEE International Symposium on Emerging Metaverse (ISEMV 2025)
https://ieee-isemv.org/call-for-papers/
Submitted by Pavana Prakash

2nd IEEE International Symposium on Emerging Metaverse (ISEMV 2025),
co-located with The International Conference on Computer Vision (ICCV 2025).
October 19–20, 2025,
Honolulu, Hawaii, USA,

ISEMV 2025, organized by the IEEE Metaverse Initiative, will bring together experts from diverse fields to explore the convergence of the physical and digital worlds. The symposium will focus on critical technologies, applications, and societal impacts shaping the emerging Metaverse.

Key Dates:

• Paper Submission Deadline: May 16, 2025 (Anywhere on Earth)
• Notification of Acceptance: June 27, 2025
• Camera-Ready Submission: August 8, 2025

Topics of Interest include, but are not limited to:

• Artificial Intelligence and Large Language Models
• Extended Reality (XR), AR/VR/MR Interfaces
• Digital Twins and Cyber-Physical Systems
• Metaverse Architectures, Standards, and Interoperability
• Human-Centered Interaction and UX
• Data Processing, Visualization, and Management
• Ethical AI, Governance, and Algorithmic Safety
• Applications: Healthcare, Industry 5.0, Education (EduVerse), Smart Cities (CityVerse), and more

Submission Details:

• Paper length: 4 to 8 pages (excluding references)
• Format: IEEE conference style (LaTeX or Word)
• Accepted papers will be published in IEEE Xplore
• Authors are encouraged to share datasets via IEEE DataPort to enhance reproducibility and visibility

Submission portal: https://easychair.org
Full CFP and updates: https://ieee-isemv.org/call-for-papers/

Contact: isemv@ieee.org

Call for Papers: IISWC 2025
https://iiswc.org/iiswc2025/cfp.html
Submitted by Dmitrii Ustiugov

IEEE International Symposium on Workload Characterization (IISWC) 2025

Overview:

IISWC invites manuscripts that present original, unpublished research in all areas related to the characterization and analysis of computing system workloads, including translational research related to production-oriented commercial systems. Work focusing on emerging technologies and interdisciplinary work are especially welcome.

Important Deadlines:
Paper Submission: June 21, 2025
Rebuttal Period: July 24, 2025 – July 31, 2025
Author Notification: August 12, 2025
Camera-ready Deadline: September 1, 2025

Submission Guidelines:

• Regular Papers: 10 pages (excluding references)
• Tool and Benchmark Papers: 6-10 pages (excluding references)

Topics:

• Characterization of applications in domains including life sciences, machine learning, generative AI and LLMs, IoT, security, HPC, cloud computing, and many others
• Characterization of workloads for emerging workloads and architectures
• Characterization of OS, Virtual Machine, middleware, and library behavior
• Implications of workloads in system design
• Benchmark methodologies and suites
• Measurement tools and techniques

For full details, submission guidelines, and artifact evaluation information, please visit the conference website.

Call for Papers: PACT 2025
http://wikicfp.com/cfp/servlet/event.showcfp?eventid=185980
Submitted by Rio Yokota

The International Conference on Parallel Architectures and Compilation Techniques (PACT) 2025
Irvine, California, USA
November 3-6, 2025.

Submission Site: https://pact25.hotcrp.com

Scope
The International Conference on Parallel Architectures and Compilation Techniques (PACT) is a unique technical conference at the intersection of hardware and software, with a special emphasis on parallelism. PACT brings together researchers from computer architectures, compilers, execution environments, programming languages, and applications to present and discuss their latest research results, tools, and practical experiences.

PACT seeks submissions in two categories:
– Research Papers
– Tools and Practical Experience (TPE) Papers

Research Papers
Research papers will be evaluated by the PACT Program Committee based on:
– Relevance: The paper should align with PACT’s topics of interest.
– Novelty/Originality: The work should present new ideas or offer fresh perspectives.
– Significance: The research should address an important problem and have the potential to influence future work.
– Results: The claims should be well-supported by clear and validated results.
– Comparison to Prior Work: The paper should properly discuss existing literature, highlighting similarities, differences, and improvements.

Tools and Practical Experience (TPE) Papers
TPE papers focus on practical applications, industry challenges, and experience reports. A TPE paper must clearly explain its functionality, summarize practical experience with realistic case studies, and describe any supporting artifacts. The title of a TPE paper must include the prefix “TPE:”. TPE papers follow the same submission guidelines and are reviewed by the same Program Committee as research papers.

TPE papers will be evaluated based on:
– Originality: They should present PACT-related technologies applied to real-world problems.
– Usability: The tool or software should have broad applicability and aid PACT-related research.
– Documentation: The tool/software should be well-documented on a public website.
– Benchmark Repository: A benchmark suite should be provided for testing.
– Availability: Preference is given to tools/software that are freely available, though industry/commercial tools may be considered with justification.
– Foundations: The paper should relate to PACT’s principles, though extensive theoretical discussion is not required.

Topics of Interest
PACT welcomes submissions on topics including, but not limited to:
– Parallel architectures, including accelerators for AI and other domains
– Compilers and tools for parallel architectures
– Applications and experimental studies of parallel processing
– Computational models for concurrent execution
– Multicore, multithreaded, superscalar, and VLIW architectures
– Compiler and hardware support for reducing memory latencies
– Support for correctness in hardware and software
– Reconfigurable parallel computing
– Dynamic translation and optimization
– I/O issues in parallel computing and their application impact
– Parallel programming languages, algorithms, and applications
– Middleware and runtime system support for parallel computing
– Application-specific parallel systems
– Distributed computing architectures and systems
– Heterogeneous systems leveraging various accelerators
– In-core and in-chip accelerators and their optimization
– Applications of machine learning to parallel computing
– Large-scale data processing, including in-memory computing accelerators
– Insights from modern parallel applications for architecture and compiler design
– Neuromorphic computing as both an application and a tool for architectures and compilers
– Quantum computing architectures and compilers

Submission Guidelines
Ensure that your submission meets the following requirements:
– Format: Papers are limited to 10 pages (excluding references) in ACM 8.5” x 11” format, double-column, 9pt font (e.g., using the `sigconf` LaTeX template). The text box must not exceed 7.15” x 9” (18.2cm x 22.9cm). Templates are available on the ACM Author Gateway (https://authors.acm.org/proceedings/production-information/taps-production-workflow).
– Abstract: Papers must include an abstract of under 300 words.
– Originality: Submissions must contain original material not previously published or under review elsewhere. Material presented at workshops without copyrighted proceedings may be submitted.
– TPE Papers: Must be prefixed with “TPE:” in the title.
– Double-Blind Review: The review process is double-blind to prevent bias. Submissions must not include author names, affiliations, or self-references that reveal authorship. Prior work by the authors must be cited in the third person.
– Legibility: Figures and graphs must be readable without magnification.
– Submission Format: Papers must be submitted in PDF format.
– Supplementary Material: A single anonymized PDF may be uploaded with additional proofs, results, or datasets. Reviewers are not required to consult supplementary material.

Posters:
– Poster submissions must follow the same formatting guidelines but are limited to 2 pages.
– Papers not accepted for full presentation will automatically be considered for posters unless authors opt out in their abstract submission.
– Two-page poster summaries will be included in the conference proceedings.

Artifact Evaluation
Authors of accepted papers are encouraged to submit their artifacts for evaluation. The Artifact Evaluation Committee assesses availability, functionality, and reproducibility. Successful artifacts will receive a seal of approval in the published paper. Authors can include a 2-page Artifact Appendix in the final paper.
We encourage authors to use open-source frameworks such as Docker, OCCAM, reprozip, CodeOcean, and Collective Knowledge to improve artifact portability and reproducibility.

Camera-Ready Instructions
– Page Limit: The final version must not exceed 11 pages, with an optional 2-page Artifact Appendix.
– Extra Pages: Up to 2 additional pages may be purchased for $200 per page.

Important Dates
– Abstract Submission Deadline: April 11, 2025 April 18, 2025 (Deadline extended)
– Paper Submission Deadline: April 18, 2025 April 25, 2025 (Deadline extended)
– Rebuttal Period: June 24-27, 2025
– Author Notification: July 28, 2025
– Artifact Submission: August 8, 2025
– Camera-Ready Deadline: September 15, 2025

All deadlines are firm at midnight anywhere on Earth (AoE).

We look forward to your submissions!

Call for Papers: ACM SYSTOR 2025
https://www.systor.org/2025
Submitted by Diana Cohen (publicity chair)

The 18th ACM International Systems and Storage Conference (SYSTOR 2025)
September 8 – 9, 2025
Virtual Event

In collaboration with the 2nd Israeli Systems & AI Workshop (ISW)
September 10, 2025,
IBM Haifa, Israel

https://www.systor.org/2025

The ACM International Systems and Storage Conference (SYSTOR) is an international forum for interaction across the systems research community. The program includes innovative, peer-reviewed research papers in the broad area of systems, as well as distinguished keynote lecturers, and a poster session.
ACM SYSTOR is designed to engage academic and industrial researchers and practitioners, welcoming both students and seasoned professionals.

SYSTOR has traditionally welcomed academic and industrial papers in systems, including storage, cloud and distributed systems, networking, AI systems and systems security. SYSTOR encourages submissions that describe results from experimental system prototypes, as well as experience papers describing practical deployments and valuable lessons learned from them.

Topics of interest include, but are not limited to:

• NEW: Systems for AI
• NEW: AI for systems management
• Sustainability/carbon footprint of computer and network systems
• System security and trust
• Big Data infrastructure
• Cloud, edge, data center, and distributed systems
• Embedded and real-time systems
• Fault tolerance, reliability, and availability
• File and storage systems
• Networked, mobile, wireless, peer-to-peer, and sensor systems
• Operating systems, computer architecture, and their interactions
• Performance evaluation and workload characterization
• Runtime systems and compiler/programming-language support
• System deployment, usage, and experience
• System design or adaptation for emerging storage technologies
• Virtualization and containers
• Storage 3.0

SYSTOR Tracks

• Full Papers Track – original research, at most 12 pages, excluding references
• Short Papers Track – original research, at most 5 pages, excluding references
• Posters with Extended Abstract Track – original work presented as a poster, accompanied by an extended abstract in the conference proceedings (accepted posters can opt-in for physical presentation at the Israeli System Workshop in person, SYSTOR physical attendance is not mandatory)

The Israeli Systems & AI Workshop:

• Highlight Papers – papers recently accepted at top-tier conferences (physical attendance required)

Important Dates (AoE)

• Full and Short Papers Track
  • Paper Submission: May 20, 2025
  • Acceptance Notification: July 10, 2025
  • Camera-ready: August 21, 2025
• Posters with Extended Abstract Track
  • Poster & Abstract Submission: July 3, 2025
  • Acceptance Notification: July 17, 2025
  • Camera-ready: August 21, 2025
• SYSTOR Virtual Conference: September 8-9, 2025
• The Israeli Systems & AI Workshop: September 10, 2025

Organizing Committee 

Program Chairs:
Pramod Bhatotia (TU Munich, Germany)
Binoy Ravindran (Virginia Tech, USA)

General Chairs:
Amit Golander (Tel Aviv University, Israel)
Joel Nider (UnifabriX, Israel)

Call for Papers: LCTES 2025
https://pldi25.sigplan.org/home/LCTES-2025
Submitted by Seonyeong Heo

26th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2025).
co-located with PLDI 2025
16 – 20 June 2025
Seoul, South Korea

LCTES provides a link between the programming languages and embedded systems engineering communities. Researchers and developers in these areas are addressing many similar problems but with different backgrounds and approaches. LCTES is intended to expose researchers and developers from either area to relevant work and interesting problems in the other area and provide a forum where they can interact. Research papers on innovative techniques are welcome, as well as experience papers on insights obtained by experimenting with real-world systems and applications.

We enthusiastically look forward to your submissions on programming languages, compilers, tools, theory, and architectures that help in overcoming technical challenges in embedded systems and their emerging applications.

Important Dates:

• Abstract Submission: March 7, 2025 March 14, 2025 (soft, open until March 21)
• Paper Submission: March 14, 2025 March 21, 2025
• Paper Notification: April 21, 2025
• Artifact Evaluation Submission: April 28, 2025
• Artifact Evaluation Notification: May 9, 2025
• Camera-Ready Submission: May 12, 2025
• Conference Dates: June 16-17, 2025

(All times are UTC-12, or “anywhere on earth”)

Paper Categories:

• Full paper: 10 pages presenting original work (at most 2 additional pages for references and appendix)
• Poster, work-in-progress and invited paper: 4 pages papers presenting original ideas that are likely to trigger interesting discussions

Links:

• Call for papers https://pldi25.sigplan.org/home/LCTES-2025#Call-for-Papers
• Submission site: https://lctes2025.hotcrp.com/

Call for Papers: FPL 2025
https://2025.fpl.org/
Submitted by Christian Pilato

The 35th International Symposium on Field-Programmable Logic and Applications (FPL 2025)
September 1 – 5, 2025,
Leiden, The Netherlands

The International Conference on Field-Programmable Logic and Applications (FPL) was the first and remains the largest conference dedicated to the rapidly growing field of field-programmable logic and reconfigurable computing. Over the past 34 years, many key advances in reconfigurable system architectures, applications, embedded processors, design automation methods, and tools have been first published in the FPL conference proceedings. The conference brings together researchers and practitioners from academia and industry worldwide.

Submission Information

Prospective authors are invited to submit original, unpublished papers in IEEE double-column format.

– Long papers may include up to eight pages plus up to two pages for references.
– Short papers are limited to four pages plus, at most, one additional page for references.

These limits are strict; submissions exceeding them will be automatically rejected. Conference proceedings will be published in IEEE Xplore.

Submission link: https://easychair.org/conferences?conf=fpl2025.
More detailed submission information: https://2025.fpl.org/calls/call-for-papers/.

Authors of selected papers will be invited to submit extended versions for a Special Issue of ACM’s Transactions on Reconfigurable Technology and Systems (TRETS) dedicated to FPL 2025.

Important Dates

• Abstract Deadline: March 14, 2025 (AoE)
• Submission Deadline: March 21, 2025 (AoE)
• Decision Notification: May 27, 2025 (AoE)

Topics of Interest

We welcome contributions on (but not limited to) the following topics related to FPL:
– Architectures and Technology
– Application Acceleration
– Programming Models and Languages
– System Software and Environment Support
– Design Methods and Tools
– Safety-Critical Applications
– High-Performance Computing
– Security of Reconfigurable Systems
– Surveys

Organizing Committee

General Chairs:
Nele Mentens (Leiden University, The Netherlands)
Todor Stefanov (Leiden University, The Netherlands)

Program Chairs:
Mirjana Stojilovic (EPFL, Switzerland)
Dirk Stroobandt (Ghent University, Belgium)
Nusa Zidaric (Leiden University, The Netherlands)

Call for Papers: EuroSys 2026
https://2026.eurosys.org/index.html
Submitted by Jingjie Li

EuroSys is a premier international forum for presenting computer systems research, bringing together professionals from academia and industry. EuroSys 2026 seeks papers in all areas of computer systems research, including the list of topics below, that address significant problems with compelling and practical solutions. 
https://2026.eurosys.org/index.html 

Topics of Interest

• Operating systems
• Distributed systems
• Cloud computing and datacenter systems
• File and storage systems
• Networked systems
• Language support and runtime systems
• Systems security and privacy
• Dependable systems
• Analysis, testing and verification of systems
• Database systems and data analytics frameworks
• Virtualization and virtualized systems
• Systems for machine learning/machine learning for systems
• Mobile and pervasive systems
• Parallelism, concurrency, and multicore systems
• Real-time, embedded, and cyber-physical systems
• Systems for emerging hardware

Important Dates:
Spring deadline

• Paper titles and abstracts due: Thursday, May 8, 2025 (AoE)
• Full paper submissions due: Thursday, May 15, 2025 (AoE)
• Reviews available: Wednesday, July 30, 2025 (AoE)
• Author responses due: Friday, August 1, 2025 (AoE)
• Notification to authors: Friday, August 22, 2025 (AoE)
• Camera-ready deadline: Friday, September 26, 2025 (AoE)

Fall deadline

• Paper titles and abstracts due: Thursday, September 18, 2025 (AoE)
• Full paper submissions due: Thursday, September 25, 2025 (AoE)
• Reviews available: Wednesday, January 7, 2026 (AoE)
• Author responses due: Friday, January 9, 2026 (AoE)
• Notification to authors: Friday, January 30, 2026 (AoE)
• Camera-ready deadline: Friday, March 6, 2026 (AoE)

Call for Papers: ICS 2025 (Cycle 2)

Submitted by Wenqian Dong

Call for Papers: ASAP 2025
https://www.asap-2025.org/
Submitted by Hanrui Wang

36th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2025)
July 28–30, 2025,
Vancouver, BC, Canada
https://www.asap-2025.org/ 

We are excited to invite researchers and practitioners to ASAP 2025, hosted by Simon Fraser University in beautiful Vancouver, BC, Canada. ASAP continues its tradition of providing a premier forum for discussing the theory and practice of application-specific systems, architectures, and processors.

Topics of interest

• Accelerator Design, e.g., AI, big data, computational genomics, finance, network processing
• Application-Specific Instruction-Set Processors and Architectures
• Approximate and Autonomous Computing Systems
• Cloud Computing Accelerators
• Compression and Computer Arithmetic
• Cryptography and Security Architectures
• Design Methods, Tools, and Compilers for Application-Specific Systems
• Edge Computing and Cyber-Physical Systems, e.g., wireless, mobile, IoT
• Embedded Systems and Domain-Specific Solutions
• Heterogeneous Computing, e.g., embedded devices, HPC systems, data centers
• Reconfigurable and Custom Computing, e.g., FPGAs, CGRAs
• Signal and Image Processing Systems
• Simulation and Prototyping, e.g., validation, performance analysis
• System Quality Attributes, e.g., energy efficiency, fault tolerance, security
• Emerging Technologies in Systems, e.g., optical computing, 3D devices and interconnects, memristors for storage and logic, in-memory computing, quantum computing

Important Dates (Anywhere on Earth – AoE)

• Abstract Submission Deadline: February 14, 2025
• Paper Submission Deadline: February 21, 2025
• Notification of Acceptance: April 28, 2025
• Conference Dates: July 28–30, 2025
• Submission Information
  ASAP 2025 welcomes regular papers (up to 8 pages, including references) and short papers (up to 4 pages, including references).
• Submissions must follow a double-blind review process. Authors are encouraged to use the IEEE manuscript templates for LaTeX or Word.
• All accepted papers will be published in the IEEE Digital Library.
• Please submit your manuscripts via HotCRP. Detailed submission instructions will be provided on the conference website.

Call for special session proposals:
We are soliciting special session proposals for ASAP’25. Each special session should focus on a single compelling theme to the ASAP audience and typically runs 1.5-2 hours. Each proposal should not exceed two pages, describe the topic, intended audience, and must include a list of 3-4 suggested speakers with tentative talk titles (preferably) and biographical data. Note that each speaker has an option to submit an invited paper and needs to pay the registration fee in order to attend and present his/her work. Invited papers will appear in IEEE Xplore.  

Please send your special session proposals to Professor Jason Anderson (janders@ece.utoronto.ca), IEEE ASAP’25 Special Sessions Chair, by April 1, 2025.

Important Dates:
Proposal submission deadline: April 1, 2025
Notification of acceptance:     April 7, 2025
Camera-ready papers:               May 20, 2025
Conference dates:                       Jul 28-30, 2025

Organizing Committee
General Chair:
– Zhenman Fang, Simon Fraser University, Canada
Program Chairs:
– Philip Brisk, University of California, Riverside, USA
– Cong “Callie” Hao, Georgia Institute of Technology, USA
Special Session Chair
Jason Anderson, University of Toronto, Canada

We look forward to your contributions and to welcoming you to Vancouver for an engaging and inspiring ASAP 2025!

Call for Papers: MICRO 2025
https://microarch.org/micro58/
Submitted by Lieven Eeckhout

58th IEEE/ACM International Symposium on Microarchitecture (MICRO) 2025
Seoul, Korea, October 18 – 22, 2025
https://microarch.org/micro58/

The IEEE/ACM International Symposium on Microarchitecture is the premier forum for presenting, discussing, and debating innovative microarchitecture ideas and techniques for advanced computing and communication systems. This symposium brings together researchers in fields related to microarchitecture, compilers, chips, and systems for technical exchange on traditional microarchitecture topics and emerging research areas. The MICRO community has enjoyed a close interaction between academic researchers and industrial designers, and we aim to continue this tradition at MICRO-58. In 2025, MICRO will be held in Seoul, Korea.

Topics of interest
• Microarchitectural, architectural, compiler, and hybrid techniques for improving system performance, power, energy-efficiency, security, cost, complexity, programmer productivity, predictability, quality of service, reliability, dependability, scalability, or sustainability
• Processor, memory hierarchy, and storage architectures
• Multicore and multiprocessor systems
• Architecture for general-purpose graphics processing units (GPUs)
• Instruction-, thread-, and data-level parallelism
• Prediction and speculation
• Cloud and datacenter-scale computing
• IoT, mobile, and embedded architecture
• Interconnection network, router, and network interface architecture
• Accelerator-based, application-specific, and reconfigurable architectures
• Architectural support for programming languages, compilation, software development, or virtualization
• Security and privacy of architectures and systems
• Architectures for emerging technologies and applications
• Architectural support for non-volatile/persistent memory
• Quantum computing
• In-/near-memory or in-/near-storage processing
• Dependable processor and system architecture
• Approximate computing and architectural support for approximation
• Effects of circuits and technology on architecture
• Architecture modeling and simulation methodologies
• Evaluation and measurement of real computing systems

Important dates:
• Abstract submission: April 4, 2025, 11:59 PM EDT (firm deadline)
• Full paper submission: April 11, 2025, 11:59 PM EDT (firm deadline)
• Rebuttal/revision period: June 9–21, 2025
• Notification of paper acceptance: July 14, 2025

Papers should be submitted for blind review. Submissions should follow the guidelines and formatting rules specified on the conference website. Papers that violate these guidelines and rules may be returned to author(s) without review. Papers will go through a rigorous peer-review process. All accepted papers will be presented at the conference.

General Co-Chairs:
Hanjun Kim, Yonsei University
Won Woo Ro, Yonsei University

Program Co-Chairs:
Minsoo Rhu, KAIST
Radu Teodorescu, The Ohio State University

Call for Papers: International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC) 2025
https://www.mcsoc-forum.org/
Submitted by Prof. Abderazek Ben Abdallah

18th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip
Dec. 15-18, 2024
Singapore (hybrid event: in person at the venue or online)
https://www.mcsoc-forum.org/

Sponsored by IEEE, Technical Committee on Microprocessors and Microcomputers (TCMM) of the IEEE Computer Society

MCSoC-2025 aims to provide the world’s premier forum of leading researchers in the Embedded Multicore/Many-core SoCs software, tools, and applications design areas for academia and industries. From the 2018 edition, the conference targets new emerging topics related to embedded AI, ML, and manycore neuro-inspired computing and systems. Prospective authors are invited to submit their contributions. All contributions should be original and have not been copyrighted, published, submitted, or accepted for publication elsewhere. Submission of a contribution implies that at least one of the authors will have full registration to the symposium upon acceptance of his/her contribution. Through this symposium, the organizers want to develop an interdisciplinary venue to contribute to and discuss the ongoing innovations, applications, and solutions to challenging embedded and general-purpose computing and design problems. We anticipate having attendees from about 40 countries and territories. The 18th IEEE MCSoC 2025 will be a

Technical Tracks

• Embedded Multicore/Manycore SoC Programming Chair: Trong-Thuc Hoang (UEC, Japan)
• Embedded Multicore/Manycore SoC Architectures, Chair: Man Wu (Keio University, Japan)
• Embedded Multicore/Manycore SoC Design, Chair: Cristinel Ababei (Marquette Univ., U.S.A)
• Embedded Multicore/Manycore SoC Interconnection Networks, Chair: Baris Taskin (Drexel University, U.S.A)
• Embedded Multicore/Manycore SoC Systems Testing, Security and Trust, Chair: ZHENG Yue (The Chinese Univ. of Hong Kong, Shenzhen, China)
• Embedded Multicore/Manycore SoC Design Automation and Low-power Design, Chair: Stefan Holst (Kyushu Institute of Technology, Japan)
• Embedded Multicore/Manycore SoC Real-Time Systems, Chair: Yi-Chung Chen (Mediatek, U.S.A)
• Operating Systems Platforms for Real-Time Embedded Applications, Chair: Lei Yang (George Mason University, U.S.A)
• Embedded Multicore/Manycore SoC Applications, Chair: Chai-Chi Tsai (National Cheng Kung University, Taiwan)
• Embedded Hardware Acceleration of AI on the Edge, Chairs: Shaswot Shresthamali (Keio Univ., Japan), Po-Tsang Huang (NYCU, Taiwan)
• ML for Energy-Efficient, High-Performance, and Reliable Manycore Systems and Interconnects, Chairs: Md. Farhadur Reza (Eastern Illinois University, U.S.A), Hanzhi Ma (Zhejiang Univ., China)
• Chiplet-based Multicore Architecture and Design, Chairs: Jason Eshraghian (UCSC, U.S.A), Darshika G. Perera (UCCS, U.S.A)

Special Sessions and Tracks

• Performance Optimization & Auto-Tuning of Software on Multicore/Manycore Systems, Chair: Tetsuya Hoshino, Nagoya University, Japan
• Emerging Machine Learning and Deep Learning Models: Theory & Applications, Chair: Jungpil Shin (The University of Aizu, Japan)
• Emerging Technologies and Sustainability, Chairs: Chiang Liang Kok (Newcastle Australia Institute of Higher Education, Australia / Singapore), Chee Kit Ho (Cushman & Wakefield, Asia Pacific.)
• Embedded Neuromorphic Computing Systems, Chair: Khanh Dang (The University of Aizu, Japan)
• Embedded Applications and Ubiquitous Computing, Chair: Taihai Chen (Zhejiang University, China)
• Embedded Machine Learning and Data Analytics, Chairs: Kasem Khalil (University of Mississippi, USA), Qinglin Yang (SYSU, China)
• Embedded, Cyber-Physical, and IoT Systems, Chair: Bahar Farahani (Shahid Beheshti University, Iran)
• Embedded Biomedical Engineering, Chairs: Xin Zhu (Institute of Science Tokyo, Japan), Md Chowdhury (Qatar University, Qatar)
• Machine Learning and Neuromorphic Computing for Edge and IoT, Chair: Anh Vu Doan (Infineon, Germany)
• Parallel/Distributed, Grid, and Cloud Computing, chairs: Lingjun Zhao (GPNU, China), Zhishang Wang (The University of Aizu, Japan)
• Intelligent Mechatronics & Neuroprosthesis Technologies, Chair: Chun-Ming Huang (Taiwan Semiconductor Research Institute, Taiwan)
• Distributed Computing & Comm. Techniques for Emerging AI Applications, Chair: Haoli Zhao (Hebei University of Technology, China)
• Quantum Technology and Machine Learning, Chair: Deepika Saxena (The University of Aizu, Japan)
• Real-Time Natural Language Processing, Chairs: Mudar Sarem (Manara University, Syria), Xiaoming He (NJUPT, China)
• Optical Communications, Devices and Networking, Chair: Guo-Wei Lu (Kyushu University, Japan)
• Advances in Intelligent Systems and Learning Technologies, Chairs: Mohamed Hamada, Yutaka Watanobe (The Univ. of Aizu, Japan)

Workshops & Tutorials

• International Workshop on Modern Technologies for Sustainability

All paper submissions to technical tracks, special sessions, and workshops should be made online via EDAS: https://edas.info/N33173

Important Dates

• Paper submission deadline: April 30, 2025
• Acceptance notification: July 20, 2025
• Camera-ready paper: July 31, 2025
• Conference date: December 15-18, 2025 (Singapore)

Call for Papers: ICS 2025
https://hpcrl.github.io/ICS2025-webpage/call-for/call-for-papers.html
Submitted by Wenqian Dong

The 39th ACM International Conference on Supercomputing (ICS 2025)
Salt Lake City, Utah, USA
June 9th-11th, 2025
https://hpcrl.github.io/ICS2025-webpage/.

Papers are solicited on all aspects of the architecture, software, and applications of high-performance computing systems of all scales (from chips to supercomputing systems), including but not limited to:

• Processor, accelerator, memory, storage, interconnect and system architectures, including architectures based on future and emerging hardware (e.g. quantum, superconducting, photonic, neuromorphic).
• Programming languages, paradigms and execution models, including domain-specific languages and scientific problem-solving software environments.
• Compilers, runtime systems and system software, including optimization and support for hardware resources and energy management.
• High-performance algorithms and applications including machine learning and large-scale data analytics, as well as the implementation and deployment of algorithms and applications on large-scale systems.
• Tools for measurement, modeling, analysis and visualization of performance, energy, or other quantitative properties of high-performance computing systems.

Submission site: https://ics25.hotcrp.com/

Important dates
Abstract submission: January 13th, 2025
Paper submission: January 16th, 2025
Rebuttal period: February 19th to February 21st, 2025
Author notification: March 14th, 2025
Camera-ready: April 14th, 2025