This is the 1st November 2025 digest of SIGARCH Messages.
Call for Papers: ISPASS 2026
https://ispass.org/ispass2026/
Submitted by Udit Gupta
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2026)
April 26-28, 2026
Seoul, South Korea
Topics of Interest
In addition to research papers, ISPASS welcomes tool and benchmark paper submissions. The conference is an ideal forum to introduce new tools and benchmarks to the community. These papers, which can detail tools and benchmarks in the above fields of interest, will be judged primarily on their potential to enable and amplify future research, which should be clearly motivated in the paper. We expect authors of accepted tools/benchmark papers to open-source their tool/benchmark before the conference.
Important Dates
Organizers
John Kim (General Chair <jjk12@kaist.edu>)
Brandon Reagen (Program Chair <bjr5@nyu.edu>)
Call for Papers: ARCS 2026: Open-Source Architectures: From RISC-V to AI Accelerators
https://arcs-conference.org/
Submitted by Mathias Pacher
39th GI/ITG International Conference on Architecture of Computing Systems (ARCS 2026)
The ARCS conferences series has over 38 years of tradition on reporting leading-edge research in computer architecture and operating systems. New chips are designed either as general-purpose devices with a wide user portfolio in mind, or target the needs of specific applications (e.g. machine learning pipelines for deep learning workloads, mobile or embedded systems). Accordingly, they might rely on well-established architectural approaches
(CPU-like, vector extensions), or bring completely new disruptive ideas limiting energy consumption. In this landscape, ARCS stands out in hosting and presenting such concepts and ideas for versatile architectures. Nowadays, such architectures often include open-source solutions such as RISC-V or AI accelerators, which are drawing more and more attention in academia and industry. ARCS’26 aims to leverage this growing interest in such architectures to foster their development, performance, and dissemination. We welcome all contributions on hardware architectures, as well as their programming models, software stacks (operating systems, compilers…), their insertion into computing systems, and the challenges to port optimized code.
In addition to the main conference, ARCS will host:
-A special track on Organic Computing.
-A special track on Dependability and Fault Tolerance.
-A PhD forum to present the work of young doctoral students (10 page papers).
-A Group forum for new professors, individual researchers, and consortia to present their research (5 page papers).
The proceedings of ARCS 2026 will be published in the Springer Lecture Notes on Computer Science (LNCS) series. A best paper will be elected by the Program Committee, and the Participants’ Favourite Presentation Award will be chosen by the audience.
Topics of Interest
Paper submission: Authors are invited to submit original,
unpublished research papers on one or more of the following topics:
Hardware Architectures
* Reconfigurable architectures
* System-on-chip
* Parallel and distributed systems
* High performance systems
* Heterogeneous many-core architectures
* Domain-specific accelerator architectures
* Real-time and mixed-criticality systems
* I/O and non-volatile memory
* Energy-efficient architectures
* Smart network technologies
* RISC-V and open-source architectures
* AI accelerators
* Dependable and fault-tolerant architectures
Programming Models and Runtime Environments
* Programming models for heterogeneous computing
* Tools for power monitoring and performance analysis
* Operating systems, algorithms, and data structures for heterogeneous architectures
* Hypervisors and middleware for homogeneous and heterogeneous multi-/many-core computing platforms
* System management including but not limited to scheduling, memory management, power/thermal management, and RTOS
* Domain-specific languages and programming models
* Architecture-specific code generation and optimization
* Architectural simulation and emulation
Cross-sectional Topics
* Near-memory and in-memory computing
* Memory and network compression technologies
* Organic Computing
* Pervasive systems
* Autonomous systems
* Approximate Computing
* Mixed-criticality systems
* Support for safety and security
* Hardware in the loop
* Optimization and performance analysis
Call for Papers: ISCA 2026
https://www.iscaconf.org/isca2026/submit/papers.php
Submitted by Amro Awad
The 53rd IEEE/ACM International Symposium on Computer Architecture (ISCA 2026)
June 27– July 1, 2026
Raleigh, USA
The International Symposium on Computer Architecture (ISCA) is the premier forum for new ideas and experimental results in computer architecture. The conference specifically seeks particularly forward-looking and novel submissions. As with prior ISCAs, there will be a main track and an industry track. For both tracks, the dates, topics, and some review policies are presented on ISCA’s webpage: https://www.iscaconf.org/isca2026/submit/papers.php
Topics of Interest
Papers are solicited on a broad range of topics, including (but not limited to):
– Processor, memory, and storage systems architecture
– Parallelism: instruction, thread, data, multiprocessor
– Datacenter-scale computing
– IoT, mobile, edge, and embedded architecture
– Verification, testing, and correctness
– Interconnection networks, routers, and network interface architectures
– Power and energy
– Sustainable computing
– Architectures for emerging applications including machine learning and bioinformatics
– Architectural support for programming languages or software development
– Architectural support for interfacing with accelerators
– Architectural support for security, virtual memory, and virtualization
– Dependable processor and system architecture
– Architectures for emerging technologies including novel circuits, memory technologies, etc.
– Quantum computer architecture
– Architecture modeling, simulation methodologies, and tools
– Evaluation and measurement of real computing systems
– Human factors and user studies
Important Dates:
All deadlines are 11:59 PM AoE
Main Track
Abstract Deadline November 10, 2025
Full Paper Deadline November 17, 2025
Round 1 Reviews Due December 19, 2025
Round 2 Reviews Due February 13, 2026
Rebuttal/Revision Period February 16 – March 6, 2026
Industry Track
Abstract Deadline December 5, 2025
Full Paper Deadline December 12, 2025
Round 1 Reviews Due February 6, 2026
Round 2 Reviews Due n/a
Rebuttal/Revision Period February 16 – 27, 2026 (no revisions)
Decisions Released: March 27, 2026
Organizers
General Co-Chairs: James Tuck (North Carolina State University) and Huiyang Zhou (North Carolina State University)
Program Co-Chairs: Kevin Skadron (University of Virginia) and Carole-Jean Wu (Meta)
Program Chair (Industry Track): Brad Beckmann (AMD)
Call for Papers: NVMW 2026
http://nvmw.ucsd.edu/
Submitted by Hung-Wei
17th Annual Non-Volatile Memories Workshop (NVMW 2026)
UCSC Silicon Valley Extension, Santa Clara, CA, USA
(planned as an in-person event)
March 9-10, 2026
http://nvmw.ucsd.edu/
The 17th Annual Non-Volatile Memories Workshop (NVMW 2026) provides a unique showcase for outstanding research on solid-state, non-volatile memories, including devices, error coding, architectures, systems, and applications.
Topics of interest
The organizing committee solicits presentations on any topic related to non-volatile, solid-state memories.
Presentations may include new results or work that has already been published during the 18 months prior to the submission deadline.
The workshop also encourages submissions from industry experiences and innovative, work-in-progress ideas.
The industry track of NVMW 2026 will accept submissions with the goal of reflecting the trends and values of real memory hardware products, software systems, and new applications from the industry. We also encourage submissions with insightful discussions on the design philosophy and implementation strategies of real systems from industry perspectives.
The work-in-progress track will accept papers on new and crazy ideas in the domain of memory research. We will select the submissions based on their potential to inspire exciting discussions and thoughts, so it is okay if the work is not fully concluded at the time of submission.
In lieu of printed proceedings, we will post the slides and extended abstracts of the presentations online. Presentation of new work at the workshop does not preclude future publication.
Submissions to the workshops are 2-page extended abstracts.
Submission Deadline: December 12th, 2025.
To submit your work, please visit https://nvmw2026.hotcrp.com/
Organizers
General Chair: Hung-Wei Tseng (University of California, Riverside)
Program Co-chairs: Changhee Jung (Purdue University) and Wenjuan Zhu (University of Illinois at Urbana-Champaign)
Local Arrangement Chair: Heiner Litz
Steering Committee: Paul Siegel, Steven Swanson, Eitan Yaakobi, and Jishen Zhao
Call for Papers: AccML @ HiPEAC 2026
https://accml.dcs.gla.ac.uk/
Submitted by José Cano
8th Workshop on Accelerated Machine Learning (AccML)
Co-located with HiPEAC 2026
January 27, 2026
Kraków, Poland
https://accml.dcs.gla.ac.uk/
https://www.hipeac.net/2026/krakow/#/program/sessions/8255/
Recent advances in diverse AI applications have driven the rise of heterogeneous architectures to accelerate machine learning workloads. Increasing model complexity and deployment demands have spurred the development of high-productivity systems, advanced programming abstractions, specialized runtimes, and tools. Since deep learning models are memory- and compute-intensive, acceleration reduces energy use and enables edge deployment. Beyond CNNs, newer models like Vision Transformers and LLMs introduce broader computational challenges, continually testing hardware, software stacks, and abstractions—highlighting the need for dedicated forums on ML acceleration and system design.
Topics of interest:
– Novel ML/AI systems: heterogeneous multi/many-core systems, GPUs, ASICs and FPGAs;
– Software ML/AI acceleration: languages, primitives, libraries, compilers and frameworks;
– Novel ML/AI hardware accelerators and associated software;
– Emerging semiconductor technologies with applications to ML/AI hardware acceleration;
– ML/AI for the design and tuning of hardware, compilers, and systems;
– Cloud and edge ML/AI computing: hardware and software to accelerate training and inference;
– Hardware-Software co-design techniques for more efficient model training and inference (e.g. addressing sparsity, pruning, etc);
– Training and deployment of huge LLMs (such as GPT, Llama), or large GNNs;
– Computing systems research addressing the privacy and security of ML/AI-dominated systems;
Submission
Papers will be reviewed by the workshop’s technical program committee according to criteria regarding the submission’s quality, relevance to the workshop’s topics, and, foremost, its potential to spark discussions about directions, insights, and solutions in the context of accelerating machine learning. Research papers, case studies, and position papers are all welcome.
In particular, we encourage authors to submit work-in-progress papers: To facilitate sharing of thought-provoking ideas and high-potential though preliminary research, authors are welcome to make submissions describing early-stage, in-progress, and/or exploratory work in order to elicit feedback, discover collaboration opportunities, and spark productive discussions.
The workshop does not have formal proceedings.
Important Dates
Submission deadline: November 21, 2025
Notification of decision: December 5, 2025
Organizers
José Cano (University of Glasgow)
Valentin Radu (University of Sheffield)
José L. Abellán (University of Murcia)
Marco Corner (Google DeepMind)
Ulysse Beaugnon (Google DeepMind)
Juliana Franco (Google DeepMind)
Call for Papers: IEEE Micro Special Issue on Top Picks from the 2025 Computer Architecture Conferences
https://toppicks2026.hotcrp.com
Submitted by Hsien-Hsin Sean Lee
IEEE Micro will publish its annual “Top Picks from the Computer Architecture Conferences” issue in September/October 2026. This issue collects some of the most significant research papers in computer architecture based on novelty and potential for long-term impact. Any computer architecture paper published in the top conferences of 2025 (including MICRO-58) is eligible. Each Top Picks submission must be based on a single paper, not a combination of multiple papers. The Top Picks Selection Committee will recognize those significant and insightful papers that have the potential to influence the work of computer architects for years to come.
Important Dates
Eligibility
Eligible submissions include papers that make substantial contributions to computer architecture published in 2025 at the following conference venues:
Core Computer Architecture Venues: ASPLOS, ISCA, MICRO, HPCA.
Related and Cross-Disciplinary Venues: MLSys, SC, PACT, ISPASS, IISWC, ICLR, NeurIPS, CVPR, SOSP, OSDI, IEEE S&P, USENIX ATC, NSDI, and NDSS.
Papers from these venues must demonstrate clear and substantial contributions to computer architecture; submissions without such focus may be desk-rejected at the discretion of the PC Chairs.
For papers originating from other venues, authors must obtain prior approval from the Selection Committee Chairs before submission.
Submission Guidelines
To simplify reviewing, there is a mandatory format for submissions. Authors will need to upload the following two documents:
Submissions that do not follow this format will not be reviewed. The first document should contain the names of the authors with a footnote that includes the title of the original conference paper, the full name of the conference, and date of publication.
Please submit here: https://toppicks2026.hotcrp.com
Accepted Paper Guidelines
Authors of accepted papers will receive further instructions on how to prepare the final papers to conform to IEEE Micro‘s guidelines. Final papers should not exceed 6,000 words including no more than 12 references and short bios of authors, with each average-size figure counting as 250 words toward this limit. Papers must have at least 30 percent new content. Final papers will be reviewed again before publication and edited for structure, style, clarity, and readability.
Guest Editors (and Selection Committee Chair and Vice Chair)
Nam Sung Kim (Chair), University of Illinois at Urbana–Champaign
Yingyan (Celine) Lin (Vice Chair), Georgia Tech
Contact the guest editors at MicroToppicks2026 <microtoppicks2026@gmail.com>
Call for Presentations: CACHP @ PPoPP 2026
https://fastcode.org/events/coevolution-workshop/
Submitted by Bruce Hoppe
Workshop on Co-evolution of Algorithms, Compilers, and Hardware for Performance (CACHP)
Co-located with PPoPP 2026
31 January – 4 February 2026
Sydney, Australia
Achieving performance requires advances in various aspects, including algorithms, programming models, software construction, compilers, and hardware. Progress in each of these areas influences and reshapes the others. For example, a new code pattern may first appear as a hand-crafted optimization by an expert programmer, then evolve into a portable compiler transformation, and eventually inspire changes in hardware architecture or system design. Such cross-pollination drives innovation, yet opportunities for the communities to engage in joint discussion remain limited.
The workshop will be organized as a half-day event (approximately four hours). We are soliciting talk proposals to introduce recent advances as well as challenges that could shape the next generation of research. Importantly, the workshop emphasizes idea exchange rather than publication, so it does not require proceedings.
Paper Submission
All submissions must be made electronically through EasyChair (https://easychair.org/conferences/?conf=cachp26). A submission should include the abstract and a high-level description of the work covered by the proposed talk. Each talk is around 20 minutes. All submissions must include a title, an abstract, and a description of the talk, and should be no longer than one page. Authors can provide additional links to related publications. A talk can feature one or multiple publications (e.g., a series of related ones). We especially encourage work that covers novel designs of algorithms, compilers, or hardware inspired by one another. Submissions will be peer-reviewed, and accepted submissions will be invited to give talks at the workshop.
We do not have a strict format requirement since the workshop does not require proceedings. Using the ACM SIGPLAN template is recommended.
Important Dates:
Organizing Team:
For any questions, please don’t hesitate to contact any of the organizers.
Call for Workshops/Tutorials: EuroSys 2026
https://forms.gle/NnVuzMFsKFTpvJ3Z9
Submitted by Christina Giannoula
Submit your workshop & tutorial proposals for EuroSys2026
Topics include OS, distributed systems, security, AI/ML & more.
Deadline: Oct 31, 2025. Apply via: https://forms.gle/NnVuzMFsKFTpvJ3Z9
Please view the SIGARCH website for the latest postings, to submit new posts, and for general SIGARCH information. We also encourage you to visit the Computer Architecture Today Blog.
- Akanksha Jain
SIGARCH Content Editor