Call for Papers: ASBD 2016

Submitted by xiufeng Sui
http://acs.ict.ac.cn/asbd2016/
June 19, 2016

Submitted by xiufeng Sui
http://acs.ict.ac.cn/asbd2016/

Sixth Workshop on Architectures and Systems for Big Data(ASBD 2016)
in conjunction with ISCA 2016
Seoul, S. Korea
June 18, 2016
 

IMPORTANT DATES:
Submissions deadline: April 10, 2016
Author notification: April 30, 2016
 

The term “Big Data” refers to the continuing massive expansion in the data
volume and diversity as well as the speed and complexity of data processing.
The use of big data underpins critical activities in all sectors of our
society. Achieving the full transformative potential of big data in this
increasingly digital world requires both new data analysis algorithms and
a new class of systems to handle the dramatic data growth, the demand to
integrate structured and unstructured data analytics, and the increasing
computing needs of massive-scale analytics.

We are pleased to request papers for presentation at the upcoming Sixth
Workshop on Architectures and Systems for Big Data (ASBD 2016) held in
conjunction with ISCA-43. The workshop will provide a forum to exchange
research ideas related to all critical aspects of emerging analytics systems
for big data, including architectural support, benchmarks and metrics, data
management software, operating systems, and emerging challenges and
opportunities. We hope to attract a group of interdisciplinary researchers
from academia, industry and government research labs. To encourage
discussion between participants, the workshop will include significant time
for interactions between the presenters and the audience. We also plan to
have a keynote speaker and/or panel session.

Topics of interest include but are not limited to:
– Processor, memory and system architectures for data analytics
– Benchmarks, metrics and workload characterization for big data
– Accelerators for analytics and data-intensive computing
– Implications of data analytics to mobile and embedded systems
– Energy efficiency and energy-efficient designs for analytics
– Availability, fault tolerance and data recovery in big data environments
– Scalable system & network designs for high concurrency/bandwidth streaming
– Data management and analytics for vast amounts of unstructured data
– Evaluation tools, methodologies and workload synthesis
– OS, distributed systems and system management support for large-scale
analytics
– Debugging and performance analysis tools for analytics and big data
– Programming systems and language support for deep analytics
– MapReduce and other processing paradigms for analytics

We encourage researchers from all institutions to submit their work for review.
Preliminary results of interesting ideas and work-in-progress are welcome.
Submissions that are likely to generate vigorous discussion will be favored!

SUBMISSION GUIDELINES:
All papers should be submitted in PDF format, using 10 point
or larger font for text (8 points or larger for figures and tables),
total length not to exceed 6 pages.
Submission site: https://easychair.org/conferences/?conf=asbd2016

ORGANIZERS:
Workshop Co-Organizers:
Lixin Zhang, ICT/CAS China
Yungang Bao, ICT/CAS China

Program Co-Chairs:
John Kim, KAIST South Korea
Xiufeng Sui, ICT/CAS China

Program Committee:
TBD

Steering Committee:
Jian Li, Huawei
Jichuan Chang, Google
Evan Speight, IBM Research

Call for Nominations: The Rau Award 2016

Submitted by Milagros Lovos
https://www.computer.org/web/awards/rau
February 26, 2016 at 08:00

Submitted by Milagros Lovos
https://www.computer.org/web/awards/rau

The Rau Award

Established in memory of Dr. B. (Bob) Ramakrishna Rau, the award recognizes his
distinguished career in promoting and expanding the use of innovative computer
microarchitecture techniques, including his innovation in compiler technology,
his leadership in academic and industrial computer architecture, and his
extremely high personal and ethical standards.

WHO IS ELIGIBLE?
The candidate will have made an outstanding, innovative contribution or
contributions to microarchitecture, use of novel microarchitectural techniques
or compiler/architecture interfacing. It is hoped, but not required, that the
winner will have also contributed to the computer microarchitecture
community through teaching, mentoring, or community service.

AWARD:
Certificate and a $2,000 honorarium.

PRESENTATION:
This year’s award will be presented at the ACM/IEEE International Symposium
on Microarchitecture (MICRO-49), held in October 15-19, 2016 in Taipei Taiwan.

NOMINATION SUBMISSION:
This award requires 3 endorsements.
Nominations are being accepted electronically through http://www.computer.org/web/awards/rau

PAST RECIPIENT:
Robert P. Colwell – “For contributions to critical analysis of microarchitecture and
the development of the Pentium Pro processor.”

IEEE Computer Society Awards site: www.computer.org/awards
IEEE Computer Society Award Nominations site: http://awards.computer.org/

Available Now: Datacenter Design and Management (Book)

Submitted by Brent Beckley
http://www.morganclaypoolpublishers.com/catalog_Orig/product_info.php?products_id=910

Submitted by Brent Beckley
http://www.morganclaypoolpublishers.com/catalog_Orig/product_info.php?products_id=910

Datacenter Design and Management

An era of big data demands datacenters, which house the computing
infrastructure that translates raw data into valuable information. This book
defines datacenters broadly, as large distributed systems that perform
parallel computation for diverse users. These systems exist in multiple forms
(private and public) and are built at multiple scales. Datacenter design and
management is multifaceted, requiring the simultaneous pursuit of multiple
objectives. Performance, efficiency, and fairness are first-order design and
management objectives, which can each be viewed from several perspectives.
This book surveys datacenter research from a computer architect’s perspective,
addressing challenges in applications, design, management, server simulation,
and system simulation.

Call For Submissions: Championship Branch Prediction Competition

Submitted by Ronald Dreslinski
http://www.jilp.org/cbp2016/

Submitted by Ronald Dreslinski
http://www.jilp.org/cbp2016/

Championship Branch Prediction Competition
co-located with ISCA 2016
Seoul, South Korea
June 19, 2016
 

The workshop on computer architecture competitions is a forum for holding
competitions to evaluate computer architecture research topics. The fifth
JWAC workshop is organized around a competition for branch prediction
algorithms. The Championship Branch Prediction (CBP) invites contestants
to submit their branch prediction code to participate in this competition.
Contestants will be given a fixed storage budget to implement their best
predictors on a common evaluation framework provided by the organizing
committee. Please see the website for more information.

Submissions Due: May 6, 2016.

Call for Participation: ASPLOS 2016

Submitted by Changhee Jung
https://www.ece.cmu.edu/calcm/asplos2016/
April 2 to April 6, 2016

Submitted by Changhee Jung
https://www.ece.cmu.edu/calcm/asplos2016/

The Twenty First International Conference on Architectural Support
for Programming Languages and Operating Systems (ASPLOS 2016)

Atlanta, Georgia, USA
April 2-6, 2016
 

– Travel Grant Application Deadline: March 1:
https://www.ece.cmu.edu/calcm/asplos2016/grants.html

– Hotel Registration Deadline: March 11:
https://www.ece.cmu.edu/calcm/asplos2016/hotel.html

– Conference Early Registration Deadline: March 11:
https://www.regonline.com/Register/Checkin.aspx?EventID=1807654&

Call for Papers: MEMSYS 2016

Submitted by Aamer Jaleel
http://www.memsys.io
March 18, 2016

Submitted by Aamer Jaleel
http://www.memsys.io

Memory Systems Conference (MEMSYS)
Washington, DC, USA
 

IMPORTANT DATES:
Submission Deadline: March 18*, 2016
Notification: May 15, 2016
Camera-Ready: July 1, 2016
* There will be an automatic submission extension of one week
 

The memory system has become extremely important recently: memory is slow,
and this is the primary reason that computers don’t run significantly faster than
they do. In large-scale computer installations such as the building-sized
systems powering Google.com, Amazon.com, and the financial sector, memory is
often the largest dollar cost as well as the largest consumer of energy.
Consequently, improvements in the memory system can have significant impact on
the real world, improving power and energy, performance, and/or dollar cost.

Moreover, many of the problems we see in the memory system are
cross-disciplinary in nature—their solution would likely require work at all
levels, from applications to circuits. Thus, while the scope of the problem is
memory, the scope of the solutions will be much wider.

Areas of Interest

Previously unpublished papers containing significant novel ideas and technical
results are solicited. Papers that focus on system, software, and architecture
level concepts, outside of traditional conference scopes, will be preferred
over others (e.g., the desired focus is away from pipeline design, processor
cache design, prefetching, data prediction, etc.). Symposium topics include,
but are not limited to, the following:

– Memory system design from both hardware & software perspectives
– Operating system design for hybrid/nonvolatile memories
– Technologies including PCM, flash, DRAM, STT-RAM, 3DXP, etc.
– Data-movement issues and mitigation techniques
– Interconnects to support large-scale data movement
– Software & application techniques for distributed memories
– Software management techniques
– Near-memory computing
– Memory-centric programming models & compiler techniques
– Memory failure modes and mitigation strategies
– Memory and system security issues

To reiterate, papers that focus on topics outside of traditional conference
scopes will be preferred over others.

SUBMISSION GUIDELINES:
Our primary goal is to showcase interesting ideas that will spark conversation
between disparate groups—to get applications people and operating systems
people and system architecture people and interconnect people and circuits
people to talk to each other. We accept extended abstracts, position papers,
and/or full research papers, and each accepted submission is given a 20-minute
presentation time slot. All accepted papers will be published in the ACM
Digital Library.

Submission formats:
2 page Extended Abstracts
5–6 page Position Papers
10–12 page Research Papers

Conference paper layout, no less than 9pt font in body, two-column, blind
submission, up to 15 pages in length.

All accepted submissions will be presented, published in the ACM Digital
Library, and included in the printed conference proceedings.

Note: Submitting either Extended Abstracts or Position Papers will not
preclude an author from submitting their work, in a longer research format,
to another publication forum at a later date.

ORGANIZERS:
Bruce Jacob, U. Maryland
Kathy Smiley, Memory Systems
Ameen Akel, Micron
James Ang, Sandia National Labs
Yitzhak Birk, Technion
Bruce Childers, U. Pittsburgh
Zeshan Chishti, Intel
Chen Ding, U. Rochester
David Donofrio, Berkeley Lab
Wendy Elsasser, ARM
Maya Gokhale, LLNL
Thuc Hoang, NNSA/DOE
Hillery Hunter, IBM
Mike Ignatowski, AMD
Aamer Jaleel, NVIDIA
David Kaeli, Northeastern
Scott Lloyd, LLNL
Gabriel Loh, AMD
Kenneth Ma, Hynix
Richard Murphy, Micron
Mike O’Connor, NVIDIA
Petar Radojkovic, BSC
David Resnick, Sandia National Labs
Arun Rodrigues, Sandia National Labs
John Shalf, Berkeley Lab
Anouk Van Laer, U. College London
Jeffrey Vetter, Georgia Tech & ORNL
Robert Voigt, Northrop Grumman
David Wang, Inphi
Christian Weis, U. Kaiserslautern
Kenneth Wright, Rambus
Sudhakar Yalamanchili, Georgia Tech

Call for Papers: Emerging Technologies for Reconfigurable Systems in the Manycore Era

Submitted by Patti Davide
http://ati.ttu.ee/recosoc2016/index.php?page=28#2
June 27 to June 29, 2016

Submitted by Patti Davide
http://ati.ttu.ee/recosoc2016/index.php?page=28#2
Emerging Technologies for Reconfigurable Systems in the Manycore Era
Special session in Int’l Symposium on Reconfigurable Communication-centric SoC’s (ReCoSoC 2016)
Tallinn, Estonia
June 27-29, 2016
 

IMPORTANT DATES:
Abstract submission deadline: April 1, 2016
Full paper submission deadline: April 6, 2016
Author notification: May 15, 2016
Camera-ready due: June 5, 2016
 

Current multicore architectures formed by tens of processing cores will be
soon replaced by the next generation of manycore architectures with hundreds
of cores. Although manycore architectures are envisaged as the most effective
for meeting the energy and performance constraints which characterize future
applications, some technical and technology aspects start to exacerbate. Dark
silicon, memory wall, on-chip communication scalability, represent just a
short list. Emerging technologies, novel architectures and design techniques,
which stress the reconfiguration concept, are currently investigated by the
research community as viable opportunities for tackling the
performance-in-the-energy-envelop problem in the manycore era.

The aim of this Special Session is to bring together a group of leading
academic researchers and technology experts to provide a platform for
discussion on novel ideas and studies related to design, modelling and
analysis of reconfigurable manycore architectures based on emerging
technologies.

SUBMISSION:
Authors are invited to submit contributions as maximum 8 page papers in IEEE
conference format. ReCoSoC 2016 follows a double-blind review process:
author’s should not reveal their identity in the manuscript. Contribution(s)
have to be submitted electronically through the EasyChair portal of the
conference at http://www.recosoc.org/

SPECIAL SESSION CHAIRS:
Davide Patti, Univ. of Catania, Italy,
Maurizio Palesi, Univ. of Enna – KORE, Italy,

Call for Nominations: Eckert-Mauchly Award

Submitted by Milagros
http://awards.computer.org/
June 18 to June 22, 2016

Submitted by Milagros

http://www.computer.org/web/awards/eckert-mauchly

2016 ACM/IEEE-CS Eckert-Mauchly Award

Deadline: 30 March 2016
 

ACM and the IEEE Computer Society co-sponsor the Eckert-Mauchly Award, which
was initiated in 1979. The award is known as the computer architecture
community’s most prestigious award.

The award recognizes outstanding contributions to computer and digital systems
architecture. It comes with a certificate and a $5,000 honorarium.

The award was named for John Presper Eckert and John William Mauchly, who
collaborated on the design and construction of the Electronic Numerical
Integrator and Computer (ENIAC), the first large-scale electronic computing
machine, which was completed in 1947.

This year’s award will be presented at the 43rd International Symposium on
Computer Architecture (ISCA). ISCA will be held in Seoul, South Korea,
June 18-22, 2016.

NOMINATION GUIDELINES:
– Open to all. Do not need IEEE Membership to nominate.
– This award requires 3 endorsements.
– Self-nominations are not accepted.
Additional details at the award web site. Contact awards@computer.org for
any questions.

Committee Selection Chair:
Antonio Gonzalez, Universitat Politecnica de Catalunya

PAST RECIPIENTS:
2015 Recipient: Norman P. Jouppi, Google
“For pioneering contributions to the design and analysis
of high-performance processors and memory systems.”

2014 Recipient: Trevor Mudge, University of Michigan
“For pioneering contributions to low power computer architecture
and its interaction with technology.”

Call for Participation: MobiTools Tutorial Co-located with ISCA 2016

Submitted by Yuhao Zhu
http://mobitools.ece.utexas.edu/
June 19, 2016

Submitted by Yuhao Zhu
http://mobitools.ece.utexas.edu/

MobiTools: Tutorial on Infrastructure and Tools for Mobile Computer
Architecture Research with an Emphasis on Real System Measurement

co-located with ISCA 2016
Seoul, Korea
June 19, 2016
 

The tutorial is a step to overcome the increasing barrier of entry for
conducting mobile computer architecture research. We present a series of tools
and infrastructures that enable computer system and architecture research in
the mobile computing space. The tutorial will span three key components of
mobile computing: software, hardware, and end-users. The tools that we will
cover strongly emphasize real system measurement, including performance,
power/energy, and user QoS experience.

Being co-located with ISCA provides an opportunity to have some great invited
speakers and an exciting panel: a great opportunity to see the masterminds
behind mobile computer architecture research.

MobiTools also invites mobile research tool developers to give a thirty minute
presentation about their tool and how to conduct productive research with it.
An ideal presentation will briefly introduce the tool and its underlying
mechanisms and then walk the audience through a (possibly hands on)
“quickstart” tutorial.

Call for Papers: NOCS 2016

Submitted by John Kim
http://www.arc.ics.keio.ac.jp/nocs16
August 31 to September 2, 2016

Submitted by John Kim
http://www.arc.ics.keio.ac.jp/nocs16

10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016)
Nara, Japan
August 31 – September 2, 2016
 

IMPORTANT DATES:
Abstract registration deadline: February 12, 2016
Full paper submission deadline: February 19, 2016
Notification of acceptance : April 8, 2016
Final version due: May 18, 2016
 

The International Symposium on Networks-on-Chip (NOCS) is the premier event
dedicated to interdisciplinary research on on-chip, chip-scale, and multichip
package scale communication technology, architecture, design methods,
applications and systems. NOCS brings together scientists and engineers
working on NoC innovations and applications from inter-related research
communities, including computer architecture, networking, circuits and
systems, packaging, embedded systems, and design automation.

Topics of interest include, but are not limited to:

1. NoC Architecture and Implementation:
– Network architecture (topology, routing, arbitration)
– NoC Quality of Service
– Timing, synchronous/asynchronous communication
– NoC reliability issues
– Network interface issues
– NoC design methodologies and tools
– Signaling & circuit design for NoC links

2. NoC Analysis and Verification:
– Power, energy & thermal issues (at the NoC, un-core and/or system-level)
– Benchmarking & experience with NoC-based hardware
– Modeling, simulation, and synthesis of NoCs
– Verification, debug & test of NoCs
– Metrics and benchmarks for NoCs

3. Novel NoC Technologies:
– New physical interconnect technologies, e.g., carbon nanotubes, wireless
NoCs, through-silicon, etc.
– NoCs for 3D and 2.5D packages
– Package-specific NoC design
– Optical, RF, & emerging technologies for on-chip/in-package interconnects

4. NoC Application:
– Mapping of applications onto NoCs
– NoC case studies, application-specific NoC design
– NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
– NoC designs for heterogeneous systems, fused CPU-GPU architectures, etc
– Scalable modeling of NoCs

5. NoC at the Un-Core and System-level:
– Design of memory subsystem (un-core) including memory controllers,
caches, cache coherence protocols & NoCs
– NoC support for memory and cache access
– OS support for NoCs
– Programming models including shared memory, message passing and
novel programming models
– Issues related to large-scale systems (datacenters, supercomputers)
with NoC-based systems as building blocks

6. On-Chip Communication Optimization:
– Communication efficient algorithms
– Multi/many-core communication workload characterization & evaluation
– Energy efficient NoCs and energy minimization

Electronic paper submission requires a full paper, up to 8 double-column IEEE
format pages, including figures and references. The program committee in a
double-blind review process will evaluate papers based on scientific merit,
innovation, relevance, and presentation.

Submitted papers must describe original work that has not been published
before or is under review by another conference or journal at the same time.
Each submission will be checked for any significant similarity to previously
published works or for simultaneous submission to other archival venues, and
such papers will be rejected. Proposals for special sessions, tutorials, and
demos are invited. Paper submissions and demo proposals by industry
researchers or engineers to share their experiences and perspectives are also
welcome.

Please see the detailed submission instructions for paper submissions, special
session, tutorial, and demo proposals on the conference web site.

ORGANIZING COMMITTEE:
General Co-Chairs:
– Hideharu Amano (Keio University, Japan)
– Partha Pratim Pande (Washington State University, USA)

Technical Program Co-Chairs:
– Hiroki Matsutani (Keio University, Japan)
– Sriram Vangal (Intel, USA)

Publicity Co-Chairs:
– John Kim (Korea Advanced Institute of Science and Technology, Korea)
– Turbo Majumder (Intel, USA)
– Maurizio Palesi (Kore University, Italy)

Publication Chair:
– Umit Ogras (Arizona State University, USA)

Industry Chair:
– Yuichiro Ajima (Fujitsu Limited, Japan)

Special Sessions Co-Chairs:
– Michihiro Koibuchi (National Institute of Informatics, Japan)
– Sudeep Pasricha (Colorado State University, USA)

Tutorial Chair:
– Paul Bogdan (University of Southern California, USA)

Finance Chair:
– Ikki Fujiwara (National Institute of Informatics, Japan)

Registration Chair:
– Takashi Nakada (University of Tokyo, Japan)

Local Arrangements Chair:
– Shinya Takamaeda (Nara Institute of Science and Technology, Japan)