Call for Papers: MEMSYS Europe 2017

The International Symposium on Memory Systems (MEMSYS Europe)
http://www.memsys.io
Frankfurt am Main, Germany
June 21–23, 2017

IMPORTANT DATES:
Submission: March 10, 2017 (There will be an automatic extension of one week)
Notification: April 14, 2017
Camera-Ready: April 28, 2017

We invite you to submit papers and talk abstracts to the inaugural MEMSYS Europe conference, to be held June 2017 in Frankfurt, Germany. MEMSYS has become the premiere US forum for research in memory systems, including hardware and software aspects, from technology and devices up to compilers and programming models. Due to popular demand for a European meeting, MEMSYS will be held in Europe this upcoming June, and you are cordially invited.

Overview:
Memory-device manufacturing, memory-architecture design, and the use of memory technologies by application software all profoundly impact today’s and tomorrow’s computing systems, in terms of their performance, function, reliability, predictability, power dissipation, and cost. Existing memory technologies are seen as limiting in terms of power, capacity, and bandwidth. Emerging memory technologies offer the potential to overcome both technology and design related limitations to answer the requirements of many different applications. The goal of this conference is to bring together researchers, practitioners, and others interested in this exciting and rapidly evolving field, in order to update each other on the latest state-of-the-art technology, exchange ideas, and discuss future challenges.

Tracks on the following topics are being organized and will be presented over the 2-day conference:
– Memory-centric programming models, programming languages, and compiler optimization
– Difficulties integrating different memory types into the software stack
– Memristors, other nonvolatile memories, and compute-in-memory technologies
– Emerging memory technologies, their controllers, and novel uses
– Memory systems, IP, SoC, controllers in automotive applications
– Interference at the memory level across datacenter applications
– Issues in the design and operation of large-memory machines
– In-memory databases and NoSQL stores
– Memory limitations in AI/ML applications and architectures
– Post-CMOS scaling efforts and memory technologies to support them, including cryogenic, neural, and heterogeneous memories

This CFP seeks papers and talks on these and other related topics.

SUBMISSION GUIDELINES:
We accept extended abstracts, position papers, and/or full research papers, and each accepted submission is given a 20-minute presentation time slot. All accepted papers will be published in the ACM Digital Library.
Submission Formats:
1–2 page Abstracts
5–6 page Position Papers
10+ page Research Papers
Conference paper layout, using ACM’s paper templates required, blind submission (no authors listed), up to 16 pages in length.

Note: Submitting either an Extended Abstract or a Position Paper will not preclude an author from submitting their work, in a longer research format, to any other publication forum at a later date.

ORGANIZERS:
Bruce Jacob, U. Maryland
Kathy Smiley, Memory Systems

Call for Papers: CoolDC’17

Workshop on Cool Topics in Sustainable Data Centers (CoolDC’17)
http://cooldc17.eecs.umich.edu
co-located with ASPLOS 2017
Xi’an, China
April 9, 2017

Submission Deadline: Feburary 10, 2017 11:59pm EST

The 2017 Workshop on Cool Topics in Sustainable Data Centers (CoolDC ’17) is a forum to disseminate results and stimulate further cutting-edge research in quantitative design, evaluation, and research methods for sustainable data centers. The goal of the workshop is to become a venue where experts in sustainable energy systems, data center physical infrastructure, networking and server architecture, cloud computing, and internet-scale applications can come together to exchange ideas on how to maintain and improve the sustainability of warehouse-scale computer infrastructure.

Topics of interest in sustainable data centers include but are not limited to:
– Instrumentation, measurement, and characterization studies
– Metrics, benchmarks, interfaces
– Performance, energy and other resource trade-offs, energy complexity
– Energy-efficient software optimization, application design
– System-level optimization, cross-layer coordination
– Scheduling, run-time adaptation, feedback control
– Processor, memory, network, storage, hardware components and architecture
– Reliability and power management
– Thermal management
– Green energy sources and their implications
– Technologies for and management of energy storage
– Life-cycle analysis

SUBMISSION GUIDELINES:
Submitted papers must be no longer than 6 single-spaced 8.5″ x 11″ pages. Please submit your papers by Feburary 10, 2017 11:59pm EST, in PDF format via the Web submission form.

ORGANIZERS:
Workshop Chairs:
Thu Nguyen, Rutgers University
Yungang Bao, ICT

Steering Committee:
Weisong Shi, Wayne State University
Thomas Wenisch, University of Michigan

Call for Participation: HPCA 2017 (early registration deadline: Jan 11)

23rd IEEE International Symposium on High-Performance Computer Architecture (HPCA)
http://www.hpcaconf.org/hpca23
co-located with PPoPP and CGO
Austin, Texas, USA
February 4-8, 2017

IMPORTANT DATES:
– Early registration deadline: January 11, 2017
– Hotel discounted rate deadline: January 11, 2017

The International Symposium on High-Performance Computer Architecture provides a high-quality forum for scientists and engineers to present their latest research findings in this rapidly-changing field. Authors are invited to submit papers on all aspects of high-performance computer architecture. Topics of interest include, but are not limited to:

– Processor, cache, and memory architectures
– Parallel computer architectures
– Multicore and multiprocessor architectures
– Impact of technology on architecture
– Power-efficient architectures and techniques
– Dependable/secure architectures
– High-performance I/O systems
– Embedded, reconfigurable, and heterogeneous architectures
– Interconnect and network interface architectures
– Architectures for cloud-based HPC and data centers
– Innovative hardware/software trade-offs
– Impact of compilers and system software on architecture
– Performance modeling and evaluation
– Architectures for emerging technology and applications

Important links:
Conference Registration: https://www.regonline.com/registration/Checkin.aspx?EventID=1904773
Hotel Reservation: https://resweb.passkey.com/go/HPCACGO17
Student Travel Grant: http://www.cs.sjsu.edu/~mak/NSF/

Sponsored by the IEEE Computer Society TC on Computer Architecture

ORGANIZERS:
General Chair:
Derek Chiou, Microsoft and UT Austin

Program Chair:
Daniel A. Jimenez, Texas A&M University

Organizing Committee:
Industrial Session Chair: Chris Wilkerson, Intel Labs
Local Arrangements Chair: Mohit Tiwari, UT Austin
Workshops and Tutorials Chair: Mike Ferdman, Stony Brook University
Finance Chair: Dam Sunwoo, ARM
Publications Chair: Xuehai Qian, USC
Travel Awards Chair: Zhenman Fang, UCLA
Publicity Chair: Michael Papamichael, Microsoft Research
Web and Submissions Chairs: Hung-Wei Tseng, UCSD and Elvira Teran, Texas A&M and Intel Labs

Call for Participation: CGO 2017 (early registration deadline: Jan 6)

International Symposium on Code Generation and Optimization (CGO)
http://cgo.org/cgo2017
co-located with HPCA and PPoPP
Austin, Texas USA
February 4-8, 2017

The International Symposium on Code Generation and Optimization (CGO) provides a premier venue to bring together researchers and practitioners working at the interface of hardware and software on a wide range of optimization and code generation techniques and related issues. The conference spans the spectrum from purely static to fully dynamic approaches, and from pure software-based methods to specific architectural features and support for code generation and optimization.

The program will feature 26 technical papers, 27 co-located workshops and tutorials, and 3 keynote speeches.

Registration, at discounted rates through January 6th:
https://www.regonline.com/builder/site/?eventid=1841528

Discounted hotel rates, through January 11th:
http://cgo.org/cgo2017/travel-information.html#hotel-info

Student travel support is available:
http://cgo.org/cgo2017/travel-grants.html

Call for Papers: Workshop on Cognitive Architectures

3rd Workshop on Cognitive Architectures (CogArch)
http://cogarch-workshop.org
co-located with ASPLOS 2017
Xi’an, China
April 9, 2017

IMPORTANT DATES
Submission deadline: February 6, 2017
Notification of acceptance: February 20, 2017
Final paper submission: March 27, 2017
Workshop date: April 9, 2017

The emerging new interest in cognitive computing has led to a paradigm shift in the field of computer architecture. The interplay between the development of state-of-the-art algorithms in cognitive sciences, computer vision, speech recognition and the design of the underlying system architectures has resulted in several cross-disciplinary advances.

After highly successful editions of the Workshop on Cognitive Architectures in 2015 and 2016, in this year’s edition we expect to consolidate the many recent works in this field and provide concrete roadmaps as to what subsequent directions the research in this field should take. This workshop proposes to bring together researchers and practitioners within systems architecture, computer vision, artificial intelligence and robotics to discuss the latest ideas, applications and commercialization strategies around the cognitive computing theme. In addition, it also aims to foster an interest into such emerging fields among industry and academic researchers alike.

CALL FOR CONTRIBUTIONS:
Recent advances in Cognitive Computing Systems (as evidenced by innovations like Watson from IBM and AlphaGo from Google DeepMind), coupled with neurally-inspired hardware designs (such as the IBM TrueNorth chip and Tensor Processing Units (TPU) from Google), have spawned new research and development activity in machine learning, neuromorphic and other brain-inspired computing models, and architectures for efficient support of complex tasks in computer vision, speech recognition and artificial intelligence. The proliferation of mobile computing platforms, Internet-of-Things and cloud support features thereof have opened up exciting new opportunities for real-time, mobile (distributed or swarm-driven) cognition. This half-day workshop solicits formative ideas and new product offerings in this general space. Topics of interest include (but are not limited to):

1. Algorithms in support of cognitive reasoning: recognition, intelligent search, diagnosis, inference and informed decision-making.
2. Swarm intelligence and distributed architectural support; brain-inspired and neural computing architectures.
3. Prototype demonstrations of state-of-the-art cognitive computing systems.
4. Accelerators and micro-architectural support for cognitive computing.
5. Cloud-backed autonomics and mobile cognition: architectural and OS support thereof.
6. Resilient design of distributed (swarm) mobile cognitive architectures.
7. Energy efficiency, battery life extension and endurance in mobile, cognitive architectures.
8. Case studies and real-life demonstrations/prototypes in specific application domains: e.g. Smart homes, connected cars and UAV-driven commercial services, as well as applications of interest to defense and homeland security.

The workshop shall consist of short presentations by authors of selected submissions. In addition, it will include invited keynotes by eminent researchers from industry and academia as well as interactive panel discussions to kindle further interest in these research topics.

SUBMISSION GUIDELINES:
Submitted papers will be reviewed by a workshop Program Committee, in addition to the organizers. While these peer-reviewed papers will not be published in the ASPLOS conference proceedings, the authors of the accepted papers will be invited to submit their work to a special issue of an eminent journal. (Presenters at the 2016 edition of CogArch were invited to submit their work to the IEEE MICRO Special Session on Cognitive Architectures).

Full paper manuscripts must be in English of up to 6 pages (with same formatting guidelines as main conference). Visit the workshop web site for further details.

ORGANIZERS:
Jingwen Leng, Shanghai Jiao Tong University, China
Karthik Swaminathan, IBM T.J Watson Research Center
Augusto Vega, IBM T.J Watson Research Center
Alper Buyuktosunoglu, IBM T.J Watson Research Center
Pradip Bose, IBM T.J Watson Research Center

Call for Papers: Cluster 2017

2017 IEEE International Conference on Cluster Computing (Cluster 2017)
https://cluster17.github.io
Honolulu, Hawaii, USA
September 5-8, 2017

IMPORTANT DATES:
– Abstract deadline: April 24, 2017 (AOE)
– Full Papers due: May 1, 2017 (Potential 7-10 days extension) (AOE)
– Acceptance Notification: June 30, 2017

IEEE Cluster 2017 is the 19th edition of the IEEE Cluster conference series, organized in cooperation with SIGHPC. Following the successes of previous IEEE Cluster conferences, we again solicit high-quality original work that advances the state-of-the-art in clusters and closely related fields. All papers will be rigorously peer-reviewed for their originality, technical depth and correctness, potential impact, relevance to the conference, and quality of presentation. Research papers must clearly demonstrate novel research contributions while papers reporting experiences must clearly describe lessons learned and impact, along with the utility of the approach compared to previous ones.

2017 Highlight: Convergence of Big Data and High-Performance Computing. While the tools and cultures for High-Performance Computing and Big Data Analytics have evolved in divergent ways, both rely on cluster architectures. As we witness an increasing awareness that further progress in scientific research depends on both areas, the interoperability and scaling convergence of these two ecosystems is expected to be critical to the future. Therefore, we have chosen this year to highlight research topics in all areas expected to bring progress in understanding if, why and how clusters should support this convergence. Specific topics are dedicated to this direction within all conference areas alongside more traditional topics.

Area 1: Application, Algorithms, and Libraries
– HPC and Big Data application studies on large-scale clusters
– Applications at the boundary of HPC and Big Data
– New applications for converged HPC/Big Data clusters
– Performance modeling and measurement
– Hybrid programming techniques (e.g., MPI+OpenMP)
– Cluster benchmarks
– Performance evaluation tools

Area 2: Architecture, Network/Communications, and Management
– Node and system architecture for HPC and Big Data clusters
– Architecture for converged HPC/Big Data clusters
– Energy-efficient cluster architectures
– Packaging, power and cooling
– Accelerators/ManyCores and heterogeneous clusters
– Interconnect/memory architectures
– Single system/distributed image clusters

Area 3: Programming and System Software
– Cluster system software/operating systems
– Programming models for converged HPC/Big Data systems
– Cloud-enabling cluster technologies and virtualization
– Resource and job management
– Fault tolerance and high-availability

Area 4: Data, Storage, and Visualization
– Cluster architectures for Big Data storage and processing
– Cluster-based cloud architectures for Big Data
– Storage systems supporting the convergence of HPC and Big Data processing
– File systems and I/O libraries
– Support and integration of non-volatile memory

SUBMISSION GUIDELINES:
Authors must indicate the primary area of preference out of the four areas above (see online for a more detailed list). They may optionally rank the other areas. The paper may be accepted as a full 10-page paper, or the committee might decide to accept it as a short paper with 4 pages in the proceedings. Note: references are not counted in the above limits on the number of pages.

Submitted papers must conform to the following IEEE Xplore layout, page limit, and font size:
– Submissions must be in PDF format.
– Submissions are required to be within 10 pages (Not counting references).
– Submissions must be single-spaced, 2-column numbered pages in IEEE Xplore format (8.5×11-inch paper, margins in inches — top:0.75, bottom:1.0, sides:0.625, and between columns:0.25, main text:10pt).
– Submissions are NOT double-blind. Author information can be included on the submission and will be visible to the reviewers.
– LaTeX and Word Templates are available here: http://www.ieee.org/conferences_events/conferences/publishing/templates.html
– Only web-based submissions are allowed via https://easychair.org/conferences/?conf=ieeecluster2017

ORGANIZERS:
General Co-chairs:
Naoya Maruyama, Riken, Japan
Todd Gamblin, Lawrence Livermore National Laboratory, USA

Program Co-chairs:
Gabriel Antoniu, INRIA, France
Richard Vuduc, Georgia Institute of Technology, USA

Area Chairs
Michela Taufer, University of Delaware, USA and Aparna Chandramowlishwaran, University of California, Irvine (Area 1)
Frank Mueller, North Carolina State University, USA (Area 2)
Kenjiro Taura, University of Tokyo, Japan (Area 3)
Maria Perez, Universidad Politecnica de Madrid, Spain and Robert Sisneros, UIUC, USA (Area 4)

Local Arrangements Chairs:
Henri Cassanova, University of Hawaii, USA
Lipyoew Lim, University of Hawaii, USA

Call for Papers: NOCS 2017

11th IEEE/ACM International Symposium on Networks-on-Chip (NOCS)
http://www.arc.ics.keio.ac.jp/nocs17
co-located with Embedded Systems Week 2017
Seoul, South Korea
October 19-20, 2017

IMPORTANT DATES:
Abstract registration deadline: April, 24th, 2017
Full paper submission deadline: May 1st, 2017
Notification of acceptance: July 1st, 2017
Final version due: August 1st, 2017

The International Symposium on Networks-on-Chip (NOCS) is the premier event dedicated to interdisciplinary research on on-chip, chip-scale, and multichip package scale communication technology, architecture, design methods, applications and systems. NOCS brings together scientists and engineers working on NoC innovations and applications from inter-related research communities, including computer architecture, networking, circuits and systems, packaging, embedded systems, and design automation.

Topics of interest include, but are not limited to:

1) NoC Architecture and Implementation
– Network architecture (topology, routing, arbitration)
– NoC Quality of Service
– Timing, synchronous/asynchronous communication
– NoC reliability issues
– Network interface issues
– NoC design methodologies and tools
– Signaling & circuit design for NoC links

2) NoC Analysis and Verification
– Power, energy & thermal issues (at the NoC, un-core and/or system-level)
– Benchmarking & experience with NoC-based hardware
– Modeling, simulation, and synthesis of NoCs
– Verification, debug & test of NoCs
– Metrics and benchmarks for NoCs

3) Novel NoC Technologies
– New physical interconnect technologies, e.g., carbon nanotubes, wireless NoCs, through-silicon, etc.
– NoCs for 3D and 2.5D packages
– Package-specific NoC design
– Optical, RF, & emerging technologies for on-chip/in-package interconnects
– In-memory network and NoCs for new memory technologies

4) NoC Application
– Mapping of applications onto NoCs
– NoC case studies, application-specific NoC design
– NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
– NoC designs for heterogeneous systems, fused CPU-GPU architectures, etc
– Scalable modeling of NoCs

5) NoC at the Un-Core and System-level
– Design of memory subsystem (un-core) including memory controllers, caches, cache coherence protocols in NoCs
– NoC support for memory and cache access
– OS support for NoCs
– Programming models including shared memory, message passing and novel programming models
– Issues related to large-scale systems (datacenters, supercomputers) with NoC-based systems as building blocks

6) On-Chip Communication Optimization
– Communication efficient algorithms
– Communication workload characterization & evaluation
– Energy efficient NoCs and energy minimization

7) Off-Chip and Rack-Level Communication
– All aspects of inter-chip network design
– All aspects of rack-level network design

SUBMISSION GUIDELINES:
Electronic paper submission requires a full paper, up to 8 double-column IEEE format pages, including figures and references. The program committee in a double-blind review process will evaluate papers based on scientific merit, innovation, relevance, and presentation. Submitted papers must describe original work that has not been published before or is under review by another conference or journal at the same time. Each submission will be checked for any significant similarity to previously published works or for simultaneous submission to other archival venues, and such papers will be rejected. Proposals for special sessions and demos are invited. Paper submissions and demo proposals by industry researchers or engineers to share their experiences and perspectives are also welcome. Please find the detailed submission instructions for paper submissions, special session, and demo proposals at the submission page.

ORGANIZERS:
General Co-Chairs:
Axel Jantsch (Vienna University of Technology, Austria)
Hiroki Matsutani (Keio University, Japan)

Technical Program Co-Chairs:
Zhonghai Lu (KTH Royal Institute of Technology, Sweden)
Umit Ogras (Arizona State University, USA)

Special Session/Demo Chair:
Paul Bogdan (University of Southern California, USA)

Industry Chair:
Soojung Ryu (Samsung, Korea)

Finance Chair:
Sudeep Pasricha (Colorado State University, USA)

Publicity Co-Chairs:
Jose Flich (Universitat Politecnica de Valencia, Spain)
Paul Gratz (Texas A&M University, USA)
Dong Xiang (Tsinghua University, China)

Web Chair:
Akram Ben Ahmed (Keio University, Japan)

Local Arrangements Chair:
Hyung Gyu Lee (Daegu University, Korea)

Call for Papers: LCTES 2017

ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded systems (LCTES)
in conjunction with PLDI 2017
http://conf.researchr.org/track/LCTES-2017/LCTES-2017-papers
Barcelona, Spain
June 21-22, 2017

IMPORTANT DATES:
Paper submission: February 14, 2017
Author notification: March 31, 2017
Final version: April 15, 2017

LCTES provides a link between the programming languages and embedded systems engineering communities. Researchers and developers in these areas are addressing many similar problems, but with different backgrounds and approaches. LCTES is intended to expose researchers and developers from either area to relevant work and interesting problems in the other area and provide a forum where they can interact. To that end, LCTES ’17 solicits papers presenting original work on programming languages, compilers, tools, theory, and architectures that help in overcoming these challenges. Research papers on innovative techniques are welcome, as well as experience papers on insights obtained by experimenting with real-world systems and applications.

Papers are solicited on, but not limited to, the following topics in embedded systems:
– Programming language challenges, including:
      Domain-specific languages
      Features to exploit multicore, reconfigurable, and other emerging architectures
      Virtual machines, concurrency, inter-processor synchronization, and memory management
– Compiler challenges, including:
      Interaction between embedded architectures, operating systems, and compilers
      Support for enhanced programmer productivity, debugging and profiling
      Optimization for low power/energy, code and data size, and best-effort and real-time performance
– Tools for analysis, specification, design, and implementation, including:
      Hardware, system software, application software, and their interfaces
      Performance estimation, monitoring, and tuning
      Design space exploration tools
– Theory and foundations of embedded systems, including:
      Predictability of resource behaviour: energy, space, time
      Validation and verification, in particular of concurrent and distributed systems
– Novel embedded architectures, including:
      Design and implementation of novel architectures
      Workload analysis and performance evaluation
      Architecture support for new language features, virtualization, compiler techniques, debugging tools
      Architectural features to improve power/energy, code/data size, and predictability
– Mobile systems and IoT, including:
      Operating systems, compilers, and software tools for mobile and IoT devices
      Compiler and software tools for mobile and IoT systems
      Memory and IO techniques for mobile and IoT devices
– Empirical studies and their reproduction, and confirmation

SUBMISSION GUIDELINES:
Submissions must be in ACM proceedings format, 9-point type, and may not exceed 10 pages (all inclusive). Word and LaTeX templates for this format are available on the ACM website (http://www.sigplan.org/Resources/Author/). Submissions must be in PDF, printable on US Letter and A4 sized paper. To enable double-blind reviewing, submissions must adhere to two rules:
– author names and their affiliations should be omitted; and,
– references to related work by the authors should be in the third person (e.g., not “We build on our previous work …” but rather “We build on the work of …”).

However, nothing should be done in the name of anonymity that weakens the submission or makes the job of reviewing the paper more difficult (e.g., important background references should not be omitted or anonymized). Papers must describe unpublished work that is not currently submitted for publication elsewhere as discussed here. Authors of accepted papers will be required to sign an ACM copyright release.

Submission site: https://lctes17.hotcrp.com

All accepted papers will appear in the published proceedings. We expect to make a best paper award.

ORGANIZERS:
General Chair: Vijay Nagarajan, University of Edinburgh
Program Chair: Zili Shao, The Hong Kong Polytechnic University

Call for Papers: FCCM 2017

25th International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)
http://fccm.org
Napa, CA USA
April 30-May 2, 2017

IMPORTANT DATES:
– Full Paper Submission Deadline: January 11, 2017 (extended)
– Short Paper Submission Deadline: January 18, 2017 (extended)
– Notification of Acceptance: March 1, 2017

The IEEE Symposium on Field Programmable Custom Computing Machines (FCCM) is the original and premier forum for presenting and discussing new research related to computing that exploits the unique features and capabilities of FPGAs and other reconfigurable hardware. For 25 years, FCCM has been the place to present papers on architectures, tools, and programming models for field programmable custom computing machines and applications that use such systems. Papers are solicited on the following topics related to Field Programmable Custom Computing Machines (FCCMs):

Abstractions, Architectures, and Programming Models:
– Novel reconfigurable architectures, including overlay architectures
– Architectures for high performance and/or low power computing
– Security enhancements for reconfigurable computing
– Volatile and non-volatile memory subsystems; stacked/hybrid memory cubes
– Clusters or large systems of reconfigurable devices

Tools:
– Abstractions, programming models, and runtimes, including virtualization
– New languages and design frameworks for spatial or heterogeneous applications
– High-level synthesis and designer productivity in general
– Software-Defined-systems (SDN, SDR, frameworks for new domains)

Reconfiguration:
– Run-time management of reconfigurable hardware
– System resilience/fault tolerance for reconfigurable hardware
– Evolvable, adaptable, or autonomous reconfigurable computing systems
– Security implications of run-time reconfiguration

Applications:
– Applications built using new high level synthesis technologies
– Data center/cluster with reconfigurable applications
– New uses of run-time reconfiguration in applications-specific systems
– Applications that utilize reconfigurable technology for performance and efficiency
– Novel use of state-of-the-art commercial FPGAs

SUBMISSION GUIDELINES:
FCCM will accept 8-page papers for oral presentation and 4-page short papers for short oral and poster presentation. FCCM uses a double blind reviewing system. Manuscripts must not identify authors or their affiliations. An online submission link will be available on the FCCM website in late December. Papers should use the formatting template linked at the FCCM website.

Authors are encouraged to submit preliminary work using the 4-page format. This category is intended for new projects and early results. These submissions will be accepted one week later than the 8-page papers.

FCCM reviews submissions in two, separate streams: 8-page papers for oral presentation and 4-page papers for brief oral and poster presentation. Both appear in the published proceedings. All submissions are reviewed in English. Papers must meet the IEEE guidelines to be reviewed and published; links to templates are at the FCCM website.

FCCM 2017 will continue the tradition of having a best paper award. We will also invite the authors of the best papers to extend their work to be considered for publication in a special section of ACM’s Transactions on Reconfigurable Technology and Systems (TRETS) for FCCM 2017. Send in your best work for consideration!

ORGANIZERS:
General Chair: Jason D. Bakos, University of South Carolina
Program Chair: Ron Sass, UNC-Charlotte
Finance Chair: Ken Eguro, Microsoft Research
Publications Chair: Greg Stitt, University of Florida
Sponsorships Chair: Jan Gray, Gray Research LLC
Publicity Chair: Kyle Rupnow, UIUC
Exhibitions and Demo Night: Nachiket Kapre, University of Waterloo

Call for Papers: FPL 2017

27th International Conference on Field Programmable Logic and Applications
http://www.fpl2017.org
Ghent, Belgium
September 4-8, 2017

IMPORTANT DATES:
Abstract and Title Submission Deadline (mandatory): March 19, 2017
Full Paper Submission Deadline: March 26, 2017

The International Conference on Field-Programmable Logic and Applications (FPL) was the first and remains the largest conference covering the rapidly growing area of field-programmable logic and reconfigurable computing. During the past 26 years, many of the advances in reconfigurable system architectures, applications, embedded processors, design automation methods and tools were first published in the proceedings of the FPL conference series. The conference objective is to bring together researchers and practitioners from both academia and industry and from around the world.

Contributions within (but not limited to) the following five conference tracks are welcome:
– Architectures and Technology
– Applications and Benchmarks
– Design Methods and Tools
– Self-aware and Adaptive Systems
– Surveys, Trends and Education

SUBMISSION GUIDELINES:
Authors are invited to submit original and unpublished contributions as 6 page papers in IEEE double column format to be considered as regular papers. Submissions accepted as posters will have 4 pages and extended abstracts for PhD forum contributions appear with 2 pages in the proceedings. The conference proceedings will be published at IEEE Xplore. Authors of selected papers will be invited to submit extended versions to a special issue in ACM TRETS. All contributions must be submitted electronically in PDF format.

FPL’s PhD forum is intended as a venue for PhD students to present their work in progress and preliminary results in a special poster session to receive feedback from other researchers.

Use the SoftConf submission site (https://www.softconf.com/g/fpl2017/) to submit your paper. Please note that the submission of the full- and short-paper abstracts by the relevant deadline is mandatory and that deadlines are not going to be extended.

ORGANIZERS:
General Co-chairs
Dirk Stroobandt, Ghent University
Nele Mentens, KU Leuven

Program Co-chairs
Marco Santambrogio, Politecnico di Milano
Diana Göhringer, Ruhr University Bochum