Call for Workshops and Tutorials: ISPASS 2017

IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2017)
San Francisco Bay Area, California, USA
April 23-25, 2017

– Deadline for submission: December 1, 2016, 11:59 PM EDT
– Notification of acceptance: December 8, 2016

The 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2017) is seeking proposals for workshops and tutorials to accompany the conference. Workshops and tutorials will be held on Sunday, April 23, and may be a half day or a full day in length.

We encourage members of the community to consider submitting proposals for workshops and tutorials that bring together researchers and practitioners working on research topics of significant current interest to the ISPASS community.

Prospective workshop and tutorial organizers are invited to submit proposals by completing the online submission form:

Selection committee:
The workshop proposals will be evaluated by members of the ISPASS 2017 organizing committee.

For questions, please contact the Workshops and Tutorials chair, Michael Ferdman (

Call for Papers: SPAA 2017

29th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA 2017)
co-located with PODC 2017
Washington D.C., USA
July 24 – 26, 2017

– Submission deadline for Regular papers: February 9, 11:59pm EDT
– Submission deadline for Brief announcements: February 9, 11:59pm EDT
– Rebuttal period: March 27-30, 11:59pm EDT
– Notification: April 23
– Camera-ready copy due: May 23

Submissions are sought in all areas of parallel algorithms and architectures, broadly construed, including both theoretical and experimental perspectives. Topics of interest include, but are not limited to:
– Parallel and Distributed Algorithms
– Parallel and Distributed Data Structures
– Algorithmic Game Theory
– Scheduling in Parallel Systems
– Parallel/Distributed Issues in Big Data
– Parallel and Distributed Architectures and I/O
– Streaming Algorithms
– Collaborative Learning Algorithms
– Network Algorithms
– Algorithms for Social Networks
– Multiprocessor and Multicore Architectures
– Transactional Memory Hardware and Software
– Algorithms for GPUs and Other Alternative Parallel Architectures
– High-Performance Parallel Computing and Architectures
– Green & Power-Efficient Algorithms and Architectures
– Instruction Level Parallelism and VLSI
– Biological Distributed Algorithms
– Mobile, Ad-Hoc, Wireless and Sensor Networks
– Algorithms for Routing and Information Dissemination
– Peer-to-Peer Systems
– Compilers and Tools for Concurrent Programming
– Fault-tolerance and Reliability
– Self-stabilization and Self-organization
– Security and Privacy in Distributed and Parallel Systems
– Parallel/Distributed Computational Learning
– Parallel Complexity Theory
– Specification and Verification of Concurrent Systems
– Resource Management and Awareness

Regular papers should report on original research, submitted exclusively to this conference. Submissions may not exceed ten (10) single-spaced double-column pages. (Papers will be judged based on their quality and not their length — short papers are welcome.) The title page, bibliography and designated figure pages (containing only figures) are not counted toward the ten pages. (Illustrative figures are encouraged.) All necessary details to substantiate the main claims of the paper should be included in a clearly marked appendix. Regular papers will be allotted up to 10 pages in the proceedings.

SPAA also solicits brief announcements that raise issues of interest to the SPAA community. Brief announcements may not exceed three pages and their titles should start with “Brief Announcement:’’. Examples of good brief announcements include: (i) papers previously published elsewhere of interest to SPAA, (ii) work in progress, (iii) announcement of tools/libraries, (iv) challenge problems posed to the community, (v) corrections to earlier results. Brief announcements may also include smaller results of interest.

All regular rejected papers automatically will be considered for brief announcements. Titles of regular papers which do not want to be considered for this option should start with “Full Paper ONLY:’’. Brief announcements will be allotted up to 3 pages in the proceedings.

Submitted manuscripts may not exceed ten (10) single-spaced double-column pages for regular papers and three (3) single-spaced double-column pages for brief announcements, using 10-point size font on 8.5×11 inch pages, not counting the title page, bibliography and designated figure pages ). The title page should contain the title, author names and affiliations, followed by a brief abstract. See (version 2.8, May 2015)
for details, including the sig-alternate-05-2015.cls style file and a sample file. Additional details may be added in a clearly marked appendix that will be read at the discretion of the program committee. Please indicate in the title of your manuscript whether this is a regular paper or a brief announcement.

Regular papers submitted to SPAA may not be under simultaneous consideration for a journal or any conference or workshop with published proceedings (other than as a brief announcement for a previous conference).
Authors are encouraged to post full versions of their submissions in a freely accessible on-line repository such as the arxiv, the ECCC, or the Cryptology ePrint archive. We expect that authors of accepted regular papers will make full versions of their papers, with proofs, available by the camera-ready deadline. (This should be done in a manner consistent with the ACM Copyright Policy.)
The deadline for ALL submissions is February 9.


General Chair:
Christian Scheideler, University of Paderborn

PC Chair:
Mohammad T. Hajiaghayi, University of Maryland, College Park

Program Committee:
Umut Acar Carnegie Mellon University
Susanne Albers Technical University of Munich
Hossein Asadi Sharif University of Technology
Nikhil Bansal Eindhoven University of Technology
Hossein Bateni Google Research
Petra Berenbrink Simons Fraser University
Keren Censor-Hillel Technion
Hubert Chan The University of Hong Kong
Rajesh Chitnis Weizmann Institute of Science
Frank Dehne Carleton University
Martin Farach-Colton Rutgers University
Pierre Fraigniaud CNRS and University Paris Diderot
Mohsen Ghaffari ETH Zurich
Michael Goodrich University of California, Irvine
Fabrizio Grandoni IDSIA
Mohammad Hajiaghayi (chair) University of Maryland, College Park
Martin Hoefer MPI Informatik, Saarbrücken
Samir Khuller University of Maryland
Ravi Kumar Google Research
Silvio Lattanzi Google Research
Aleksander Madry MIT
Friedhelm Meyer auf der Heide Paderborn University
Vahab Mirrokni Google Research
Morteza Monemizadeh Rutgers University
Seffi Naor Technion
Boaz Patt-Shamir Tel Aviv University
Giuseppe Persiano Università di Salerno
Cynthia A Phillips Sandia National Laboratories
Yuval Rabani The Hebrew University of Jerusalem
Rachid Guerraoui EPFL
Harald Raecke TU München
Rajmohan Rajaraman Northeastern University
Mauricio Resende Amazon
Laura Sanità University of Waterloo
Alex Slivkins Microsoft Research, NYC
Peter Varman Rice University
Roger Wattenhofer ETH Zurich
Ryan Williams Stanford University and MIT
David Woodruff IBM Almaden Research Center

Call for Contributions: Workshop on Pioneering Processor Paradigms

Call for Contributions: First Workshop on Pioneering Processor Paradigms (WP3)
in conjunction with HPCA’16
Austin, Texas, USA
February 4, 2017

– Submission deadline: November 27, 2016
– Notification of acceptance: December 11, 2016
– Final paper submission: January 8, 2017
– Workshop date: February 4, 2017

In trying to forge a path of innovation, it is sometimes worth examining the past to look for major paradigm shifts in (micro)-architecture, circuits, modeling and software that helped us keep going in the face of past technology-driven disruption points. With this in mind, we present a new workshop pioneering processor paradigms (P3). With the help of true pioneers as well as budding new researchers, P3 will take a retrospective look at how past technological hurdles were circumvented through major innovations. The goal is to learn from the past in devising new solution strategies for the future.

The P3 workshop will offer a number of invited talks from true pioneers as well as reviewed selections from the new generation of researchers and teachers who are eager to take a retrospective look into surveying past pioneering work that can teach us a lesson about solution strategies of the future.

The workshop on pioneering processor paradigms invites survey (or tutorial)-like submissions for review. The ideal paper would highlight a single pioneering paper (or set of papers) constituting a major processing, design, modeling or software paradigm shift in the past. In addition to explaining the context and basic concepts articulated in such work, the author(s) should draw relevant conclusions about how this pioneering work could or should influence computing paradigms of the future.

Note: Ph.D dissertation research topic proposals from (junior graduate students) that contain a survey of a key paper or two to build up the motivational justification of the proposal are quite welcome, for example.

Example topic areas include (but are not limited to):
– Processing and cache taxonomy papers.
– RISC architectures and CISC-to-RISC dynamic translation support.
– Processor pipelining, super scalar processing and branch prediction innovations.
– Register renaming, out-of-order execution and precise interruption.
– Cycle-accurate processor performance modeling.
– Innovations in floating point arithmetic units and vector/SIMD acceleration.
– VLIW architectures.
– Multi-threading, multiscalar and speculative multi-threading.
– Homogeneous and heterogeneous multi-core processors; accelerator-enabled efficiency boost.
– Power, temperature, and reliability-aware computing – with associated modeling innovations.
– Compiler innovations in support of novel microarchitectural paradigms.
– Circuit design innovations in support of (micro)-architectural paradigm shifts.

John-David Wellman, IBM
Robert Montoye, IBM
Ramon Bertran, IBM
Pradip Bose, IBM

Call for Papers: ISCA 2017

The 44th ACM/IEEE International Symposium on Computer Architecture (ISCA)
Toronto, ON, Canada
June 24-28, 2017

– Abstract Deadline: November 11, 2016, 11:59:59PM EST (Mandatory)
– Final Submission Deadline: November 18, 2016, 11:59:59PM EST no extensions
– Rebuttal Period: Early/mid February, 2017
– Author Notification: March 8, 2017
– Final Manuscript Submission: May 1, 2017
– Early Registration Deadline: May 1, 2017

Submissions Site:

The International Symposium on Computer Architecture is the premier forum for new ideas and experimental results in computer architecture. The conference specifically seeks particularly forward-looking and novel submissions. Papers are solicited on a broad range of topics, including (but not limited to):
– Processor, memory, and storage systems architecture
– Parallel and multicore systems
– Data-center scale computing
– Architectures for handheld and mobile devices
– Application-specific, reconfigurable, or embedded architectures
– Accelerator-based architectures
– Architectures for security and virtualization
– Power and energy efficient architectures
– Interconnection networks
– Instruction, thread, and data-level parallelism
– Dependable architectures
– Architectural support for programming productivity
– Network processor and router architectures
– Architectures for emerging technologies and applications
– Effect of circuits and technology on architecture
– Architecture modeling and simulation methodology
– Performance evaluation and measurement of real systems

– General Chair: Andreas Moshovos, University of Toronto
– Program Chair: David Brooks, Harvard University
– Finance Chair: Mike Ferdman, University of New York, Stony Brook
– Tutorials Chair: Paul Gratz, Texas A&M
– Workshops Chair: TBD
– Publicity Chair: Christina Delimitrou, Cornell University
– Web and Social Media Chair: Gennady Pekhimenko, MSR and University of Toronto
– Publications Chair: Mahdi Bojnordi, University of Utah
– Student Travel Awards Chair: Natalie Enright Jerger, University of Toronto
– Registrations Chair: Adrian Sampson, Cornell University
– Industry Laison Chair: José F. Martínez, Cornell University

Program Committee:
Aamer Jaleel – Nvidia
Abdullah Muzahid – UT San Antonio
Abhishek Bhattacharjee – Rutgers
Adrian Sampson – Cornell
Alper Buyuktosunoglu – IBM
Antonia Zhai – U.Minnesota
Antonio Gonzalez – UPC
Babak Falsafi – EPFL
Benjamin Lee – Duke
Carole-Jean Wu – Arizona State
Chia-Lin Yang – National Taiwan University
Chris Batten – Cornell
Chris Wilkerson – Intel
Christina Delimitrou – Cornell
Daniel Sorin – Duke University
Daniel Sanchez – MIT
Debbie Marr – Intel
Doug Burger – Microsoft
Drew Hilton – Duke
G. Edward Suh – Cornell
Emre Ozer – ARM Research
Hadi Esmaeilzadeh – Georgia Tech
James Hoe – CMU
Jangwoo Kim – POSTECH
Josep Torrellas – UIUC
Jun Yang – Pittsburgh
Jung Ho Ahn – Seoul National University
Karu Sankaralingam – Wisconsin
Kei Hiraki – U.Tokyo
Kim Hazelwood – Facebook
Koji Inoue – Kyushu University
Kunle Olukotun – Stanford
Lieven Eeckhout – Ghent Univ.
Lingjia Tang – Michigan
Lisa Wu – Berkeley
Lizy John – UT Austin
Luis Ceze – Washington
Martha Kim – Columbia
Mattan Erez – UT Austin
Michael Ferdman – Stony Brook University
Michael Taylor – UCSD
Mike O’Connor – Nvidia
Moinuddin Qureshi – Georgia Tech
Nam Sung Kim – UIUC
Natalie Enright-Jerger – U.Toronto
Omer Khan – Connecticut
Onur Mutlu – ETH
Paul Whatmough – Harvard
Paul Gratz – Texas A&M
Pierre Michaud – INRIA
Qiang Wu – Facebook
Rajeev Balasubramonian – Utah
Ramon Canal – UPC-Barcelona Tech
Ravi Iyer – Intel
Reetuparna Das – Michigan
Russ Joseph – Northwestern
Sally McKee – Chalmers University of Technology
Sandhya Dwarkadas – Rochester
Shih-Lien Lu – TSMC
Simha Sethumadhavan – Columbia/Chip Scan
Yakun Sophia Shao – Nvidia
Sreenivas Subramoney – Intel
Steve Swanson – UCSD
Tao Li – University of Florida/NSF
Vijay Janapa Reddi – UT Austin
Viji Srinivasan – IBM
Xiaoyao Liang – Shanghai Jiao Tong University
Xuehai Qian – USC
Yan Solihin – NSF/NC State
Yiannakis Sazeides – U. of Cyprus

Call for Papers: GPGPU-10

Workshop on General Purpose Computing using GPUs (GPGPU)
in conjunction with PPOPP’17
Austin, Texas, USA
February 4-8, 2017

Papers due: November 20, 2016
Notification: December 20, 2016
Final Paper Due: January 15, 2017

Now in its 10th year, the goal of this workshop is to provide a forum to discuss new and emerging general-purpose programming architectures, environments and platforms, as well as evaluate applications that have been able to harness the horsepower provided by these platforms. This year’s work is particularly interested in new heterogeneous architecture/platforms, new forms of concurrency, and novel/irregular applications that can leverage these platforms.

Papers are being sought on many aspects of GPUs, including (but not limited to):
– GPU Applications
– GPU Programming Environments
– GPU Runtime Systems
– GPU Complication
– GPU Architectures
– Multi-GPU Systems
– GPU Power/efficiency
– GPU Reliability
– GPU Benchmarking/measurements
– Heterogeneous Architectures/platforms

Full paper submissions must be in PDF formatted for US lettersize paper. They must not exceed 10 pages (all inclusive) in standard ACM two-column conference format (preprint mode, with page number). Templates for ACM format are available for Microsoft Word, and LaTeX at: (use the 9 pt template). All accepted papers will be published in the ACM Online Conference Proceedings Series.

David Kaeli, Northeastern University
John Cavazos, University of Delaware

Call for Papers: IEEE Micro Special Issue on Ultra-low-power Processors

IEEE Micro Special Issue on Ultra-low-power Processors

Guest Editors:
David Brooks, Harvard University
John Sartori, University of Minnesota

– Submissions due: April 29, 2017
– Author notification: June 17, 2017
– Revised papers due: July 15, 2017
– Final versions due: August 19, 2017
– Publication: November/December 2017

Emerging applications for connected sensing and wearable computing create robust demand for ultra-low-power (ULP) edge computing devices and associated system-on-chip (SoC) architectures. In fact, the ubiquity of ULP processing has already made such embedded devices the highest volume processor part in production, with an even greater dominance expected in the very near future. Emerging applications like the internet of everything are calling for a processor embedded in every object, and the number of processors is projected to be in the billions or trillions. At the same time, the explosion of data generated from these devices, in conjunction with the traditional model of using cloud-based services to process the data, places tremendous demands on limited wireless spectrum and energy-hungry wireless networks. Smart, ultra-low-power edge devices are the only viable option that can meet these demands.

This special issue of IEEE Micro will explore novel design techniques for ultra-low-power processors, bridging the gap between VLSI/CAD, microarchitecture, and lower levels of the compute stack, in the context of emerging applications that are driving the ultra-low-power revolution.

Areas of interest for this issue include the following.
– Application-aware design and optimization of ULP processors
– VLSI, CAD, and microarchitecture techniques for ULP processors
– Studies of new device technologies (e.g. TFETs) applied to ULP processors
– Energy harvesting approaches in conjunction with ULP processing
– Power reduction techniques for end-to-end ULP systems, including techniques that target communication costs with smarter edge computation

Log in to ScholarOne Manuscripts and submit your manuscript. Acceptable file formats are Microsoft Word document and PDF. Please direct ScholarOne questions to the IEEE Micro magazine assistant ( Manuscripts should not exceed 5,000 words, including a maximum of 12 references, with each average-­sized figure counting as 250 words. Please include all figures and tables, as well as a cover page with author contact information (name, postal address, phone, fax, and email address) and a 200­-word abstract. Accepted articles will be edited for structure, style, clarity, and readability. For more information, please visit the IEEE Micro author guidelines. Submitted manuscripts must not have been previously published or submitted for publication elsewhere, and all manuscripts must be cleared for publication. All conference papers must have at least 30 percent new content compared to the original.

Contact the guest editors at, or the EiC at

Call for Applications: The 2017 CRA-W Grad Cohort Workshop

The 2017 CRA-W Grad Cohort Workshop
Washington DC, USA
April 7-8, 2017.

Applications due: November 30, 2016

The CRA-W Grad Cohort program, initiated in 2004, is generously funded by sponsors from industry, ACM, CRA, academia, the National Science Foundation, and the computing community. Grad Cohort aims to increase the ranks of senior women in computing-related studies and research by building and mentoring nationwide communities of women through their graduate studies.

The Grad Cohort Workshop welcomes women graduate students in their first three years of graduate school into the community of computing researchers and professionals. Participants will meet for two days with 20 to 25 senior computing-related researchers and professionals, who will share pertinent information on graduate school survival skills, as well as more personal information and insights about their experiences. The rewards of a research career will be emphasized. The workshop will include a mix of formal presentations and informal discussions and social events. Through this workshop, students will be able to build mentoring relationships and develop peer networks that will form the basis for ongoing activities during their graduate careers.

Reasonable travel expenses, meals, and lodging will be provided for students chosen to participate in this program.

The Grad Cohort 2017 application is now open. Applications are due November 30th. Full details at the event web site.

For questions about the Grad Cohort program, please write to

Call for Papers: Computing Frontiers 2017

ACM International Conference on Computing Frontiers (CF’17)
Siena, Italy
May 15 – 17, 2017,

Submissions deadline: January 20, 2017
Notification: March 14, 2017
Camera-Copy Papers Due: April 4, 2017
Conference Dates: May 15 – 17, 2017

The next ACM International Conference on Computing Frontiers will be held May 15-17 in Siena, Italy. Computing Frontiers is an eclectic, collaborative community of researchers who investigate emerging technologies in the broad field of computing: our common goal is to drive the scientific breakthroughs that transform society. Technology is experiencing revolutions in memory devices and systems, networks, electronic device production, machine learning, data analytics, cloud computing, techniques to improve power and energy efficiency, systems portability/wearability, to name but a few areas. New application domains that affect everyday life are emerging, especially in this era of highly interconnected and collaborative cyber-physical systems. Boundaries between the state-of-the-art and revolutionary innovation constitute the frontiers that mark the advances of science, engineering, and information technology.

Early research that envisions future technologies provides the bases that allow novel materials, devices, and systems to become mainstream. Collaborative efforts among researchers with different expertises and backgrounds enables revolutionary scientific breakthroughs that lead to innovative solutions over a wide spectrum of computer systems, from embedded and hand-held/wearable devices to supercomputers and data centers.

We seek original research contributions at the frontiers of a wide range of topics, including novel computing paradigms, computational models, algorithms, application paradigms, development environments, compilers, operating environments, computer architecture, hardware substrates, memory technologies, and smarter life applications:

– Algorithms and Models of Computing: Approximate and inexact computing, quantum and probabilistic computing
– Biological Computing Models: Brain computing, neural computing, computational neuroscience, biologically-inspired architectures
– Limits on Technology Scaling and Moore’s Law: Defect- and variability-tolerant designs, graphene and other novel materials, nanoscale design, optoelectronics, dark silicon
– Uses of Technology Scaling: 3D stacked technology, challenges of many-core designs, accelerators, PCM’s, novel memory architectures, mobile devices
– Embedded and Cyber-Physical Systems: Design space exploration, modeling and development frameworks for interconnected systems and CPS and CPSoS, ultra-low power designs, energy scavenging, reactive and real-time systems, reconfigurable and self-aware systems, sensor networks and internet of things, and architectural innovation for wearable computing
– Big Data Analytics: High performance data analytics, data search and representation, architecture, and system design
– Machine and Deep Learning: innovative algorithms and architectures, neuromorphic approaches
– Large-Scale System Design: Homogeneous and heterogeneous architectures, runtimes, networking technologies and protocols, power- and energy-management for cloud and grid systems, data centers, exa-scale computing
– Compiler Technologies: Advanced/novel analyses, hardware/software integrated solutions, domain-specific languages, high-level synthesis
– Security: Methods, system support, and hardware for protecting against malicious code; real-time implementations of security algorithms and protocols; quantum and post-quantum cryptography; advanced persistent threats, cyber and physical attacks, and countermeasures
– Computers and Society: Education, health, cost/energy-efficient design, smart cities, and emerging markets
– Interdisciplinary Applications: Applications bridging multiple disciplines in interesting ways

We also strongly encourage submissions in emerging fields that may not fit into traditional categories. If in doubt, please contact the PC co-chairs by email.

Authors are invited to submit full papers, position papers, trend papers, and poster abstracts to the main conference. Authors must declare in advance to which category they are submitting. Full papers are a maximum of eight (8) double-column pages in ACM conference format. Authors may purchase up to two (2) additional pages at 100 Euro per page. Authors can submit full papers of up to 10 double-column pages, provided that they agree to pay for the additional pages if the paper is accepted. All other types of submissions should be at least two (2) pages and not more than four (4) pages in the same format. These limits include figures, tables, and references. Our review process is double-blind: please remove all identifying information from the paper submission (and cite your own work in the third person). Authors of interesting work not mature enough for an oral presentation may be offered the option of presenting their work as posters.

Position papers, trend papers, poster abstracts and workshop papers will be published in the proceedings and in the ACM Digital Library. As per ACM guidelines, at least one unique author of each accepted paper is required to register for the conference.

Selected papers from the Computing Frontiers 2017 conference will be invited to extend their work for publication in a special issue of the Springer Journal of Signal Processing Systems (JSPS).

General Chair:
Roberto Giorgi, University of Siena, IT

Program Co-Chairs:
Michela Becchi, University of Missouri, US
Francesca Palumbo, University of Sassari, IT

Call for Papers: Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems

2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems (AISTECS)
in conjunction with HiPEAC 2017
Stockholm, Sweden
January 25, 2017

Submission deadline: October 30, 2016
Author notification: November 15, 2016
Camera-ready papers due: November 30, 2016

The AISTECS workshop promotes research and knowledge exchange on evolutionary as well as revolutionary interconnect technologies. This includes interconnect-related topics in the perspective of their adoption in future high performance systems and, in general, within future computing systems from servers/workstations down to embedded devices and the Internet of Things, which are tied to strict power budget and thermal envelopes because of the impending green computing era. To this end, the exploration of emerging interconnect technologies along with the design of disruptive/novel ideas at the microarchitectural network level are necessary, both leading to crucial challenges and interesting design tradeoffs for their widespread adoption in next-generation computing platforms. Furthermore, we expect that novel interconnect features have the potential to constitute disruptive new ideas able to modify the expected shape of future computer systems from the design point of view and also from the programmability and/or runtime management perspectives. Finally the workshop aims to increase the synergy to develop advanced interconnect solutions and technologies for emerging computing systems from a complete range of perspectives following a holistic approach: from raw technology issues and solutions up to studies at the overall system level of modern multi-/many-core systems. This encompasses novel network solutions from both academic and industrial researchers.

Workshop Topics:
– Networks on Chip (NoCs)
– Network architectures (topology, control-flow, routing, etc.)
– Silicon Photonics and Optical NoCs
– Interconnect solutions for heterogeneous GPU/FPGA-based multi/macro-chip systems
– Communication infrastructures for HPC systems, Supercomputers and Data Centers
– Emerging interconnect technologies (EIT): photonics, carbon nanotubes, through-silicon, RF, wireless NoC.
– Crucial challenges and design tradeoffs for EIT in future computer systems
– Low-level technological improvements and implications of EIT in future communication systems
– Thermal-/energy-and power-related NoC optimization and dark silicon
– Reconfigurable/programmable interconnect components
– Efficient interconnect for 2.5D and 3D packaging
– Asynchronous interconnect designs
– Clockless interconnects with focus on automation of their design methodology
– Network infrastructures for Internet-of-Things devices
– Architectures for QoS support and coherency
– Network solutions for performance isolation in many-core systems
– Impact of the interconnect on application performance
– Reliability, availability, fault tolerance for system communication
– Programming models for communication-centric systems
– Secure interconnection networks for intra-chip and inter-chip communication
– Efficient memory networks for large-scale workloads and Big Data applications

We invite contributions of previously unpublished results on the listed areas of future interconnect-centric systems, although not limited to them. We are interested in research, experimental, systems-related, survey, perspective and work-in-progress papers in all aspects of interconnects in general and emerging interconnect technologies/paradigms in particular at all levels of development.

Papers must be in PDF format and should include title, authors and affiliations as well as the e-mail address of the contact author. Papers must be formatted in accordance to the ACM two-column style. ACM Word or LaTeX style templates will be available on the website. Submissions must be limited to 4 pages. Papers deviating significantly from the paper size and formatting rules may be rejected without review.

Accepted papers will be published in the ACM Digital Library within the ACM International Conference Proceedings Series (ICPS). Authors will be sent the ACM form and instructions to finalize the camera-ready submission and to complete the publication procedure.

General Chairs:
– Sören Sonntag (Intel, Germany)
– José Manuel Garcia Carrasco (University of Murcia, Spain)

Program Chairs:
– José Luis Abellán Miguel (Catholic University of Murcia, Spain)
– Daniel Müller-Gritschneder (TU Munich, Germany)

Publication and Web Chair:
– Marco Balboni (University of Ferrara, Italy)

Steering Committee:
– Davide Bertozzi (University of Ferrara, Italy)
– Cyriel Minkenberg (Rockley Photonics, Switzerland)

Technical Program Committee:
– Sergi Abadal, Universitat Politècnica de Catalunya, Spain
– Federico Angiolini, iNoCS, Switzerland
– José Luis Ayala, Complutense University of Madrid, Spain
– Sandro Bartolini, University of Siena, Italy
– Giorgios Dimitrakopoulos, Democritus University of Thrace, Greece
– Holger Fröning, University of Heidelberg, Germany
– Francisco Gilabert, Intel, Germany
– Ajay Joshi, Boston University, USA
– David Kaeli, Northeastern University, USA
– John Kim, KAIST, South Korea
– Sébastien Le Beux, Lyon Institute of Nanotechnology (INL), France
– Sergei Mingaleev, VPIphotonics, Germany
– Chrysostomos Nicopoulos, University of Cyprus
– Sébastien Rumley, Columbia University, USA
– Jose Luis Sanchez Garcia, University of Castilla-La Mancha, Spain
– Laurent Schares, IBM, USA
– Johana Sepúlveda, TU Munich, Germany
– Federico Silla, Universitat Politécnica de Valencia, Spain
– Eitan Zahavi, Mellanox, Israel

Call for Workshops and Tutorials: PLDI 2017

2017 ACM Conference on Programming Language Design and Implementation (PLDI)
Barcelona, Spain
June 19-23, 2017

Proposals for workshops with proceedings due: Nov 28, 2016
Acceptance Notification: Dec 9, 2016
Proposals for workshops/tutorials without proceedings due: Jan 30, 2017
Workshop and Tutorials held (tentatively): Jun 18,22,23 2017

PLDI 2017 will host co-located workshops and tutorials for which it calls for proposals. This year, PLDI is a part of a large cluster of co-located conferences including ECOOP, Curry On, LCTES, ISMM, DEBS and others. Take your chance in addressing the diverse audience of the premier forum in programming language design and implementation by proposing your event. PLDI welcomes prominent events focusing on programming language design theory and practice, for which it can provide guidance in publishing results in the ACM Digital Library.


A proposal should provide:
– Name of the workshop/tutorial.
– Duration of the workshop/tutorial.
– Organizers: names, affiliation, contact information, brief (100 words) biography.
– A short description (150-200 words) of the topic.
– Event format: workshop/tutorial; type of submissions if any; review process; results dissemination; references to previous events.
– Expected attendance and target audience within PLDI community.

Please submit proposals in plain text to Aaron Smith . Workshops that would like their proceedings included in the ACM Digital Library must submit a proposal by November 28. Proposals for co-located workshops/tutorials without formal proceedings will be accepted until January 30.

General Chair: Albert Cohen, INRIA, France
Program Chair: Martin Vechev, ETH Zurich, Switzerland