Shuang Chen is a third-year Ph.D. student in the Computer Systems Lab at Cornell University, advised by Prof. José F. Martínez and Prof. Christina Delimitrou. She is generally interested in computer architecture and systems, with a focus on datacenters and architectural support for emerging memory technologies.

Broadly speaking, I'm interested in computer architecture, particularly parallel systems. Prior work has included workload characterization of parallel applications and memory systems in traditional multiprocessor systems and GPUs. Recent work explores correctness in IoT systems.

Elaheh Sadredini is an assistant professor at the Department of Computer Science and Engineering at UC Riverside. She received her Ph.D. in Computer Science at the University of Virginia in 2019, advised by Professor Kevin Skadron, and she was a member at the Center for Research on Intelligent Storage and Processing in Memory (CRISP). Her research focus is on developing specialized, near-memory, and in-memory hardware accelerators for big data applications, including natural language processing, data mining, and bioinformatics. Her research has resulted in several publications at top-tier venues (such as MICRO, ASPLOS, HPCA, ICS, and KDD) and several patents and patent applications. Elaheh is the recipient of several awards, including the John A. Stankovic Graduate Research Award from the UVA Department of Computer Science for outstanding research in 2019 and the UVA International Students Office Graduation Award for Academic Excellence in 2019. She also received the best paper awards at the ACM International Conference on Computing Frontiers in 2016, the “Best of CAL” award in 2019, and a nomination for the best paper award at IISWC’19, FCCM’20, and HPCA’20.

Antara is doing a PhD at Computer Architecture and Dependable Systems Lab (CADSL), IIT Bombay in collaboration with the University of Tokyo. She is an Intel India PhD fellow and Google WomenTechmaker Asia-Pacific scholar. She is currently interning at Microarchitecture Research Labs (MRL), Intel India. Her areas of interest include near-data processing, 3D DRAMs, convolutional neural network, non-von Neumann architecture and related topics. She has worked on multicore cache coherence protocols during her masters at IIIT Delhi. Her work on dual-port SRAMs with ST Microelectronics was published in VDAT’16. She interned at SanDisk where she designed a digital duty cycle corrector for NAND flash high-speed interface. She has also worked in automotive electronics at TATA Motors Sanand plant.