Women in Computer Architecture (WICARCH) is designed to create a community for women studying and working in the field of computer architecture. Our goal is to promote women in computer architecture and increase visibility for their research and development contributions. We welcome participation from all women including students, post docs, industry researchers and developers and faculty members. To be listed in our directory, please click here.

Profiles of WICArch

The mission of this section is to profile women in computer architecture across many walks of our field, from [junior, senior] x [industry, academia].

If you would like to be profiled, would like to nominate someone to be profiled, or would like to write a profile, please let us know by wicarch-chair@acm.org

Mengjia Yan

Dr. Mengjia Yan is undoubtedly one of the most delightful people you will ever meet – smart, positive, exceedingly wise beyond her years, and the kind of person who can turn a frown upside down.  She was paired with me as a mentee at ISCA 2018, but I genuinely think that it is I who have benefited from the relationship.  These days, she is a new assistant professor at MIT, having recently completed her PhD at the University of Illinois at Urbana-Champaign in 2019.


WICArch Directory

We actively maintain a list of women working in the field of computer architecture.  The goal of this list is many-fold.  First, the list services as a resource for program chairs and conference organizers to identify women to serve in key technical roles such as keynote, panels and program committees.  Second, the list is designed to foster community and help women connect with other women in computer architecture.  This list can be used by current and potential graduate students to find advisors and mentors. Four profiles, selected randomly, are shown below.  We encourage you to browse the full directory.

Picture of Divya Mahajan

Divya Mahajan

PhD Candidate
Georgia Institute of Technology
Personal URL

Research Statement

I am a PhD candidate in the Computer Science Department at Georgia Institute of Technology advised by Professor Hadi Esmaeilzadeh. I received my Bachelors (2012) in Electrical Engineering from Indian Institute of Technology Ropar, India where I was honored with the President of India Gold medal for my outstanding academic performance. Subsequently, I completed my Masters (2014) from the University of Texas, at Austin in Electrical and Computer Engineering. I joined my PhD studies in Fall 2014 and since have been a part of Alternate Computing Technologies lab. My research interests include computer architecture, microarchitecture design, and developing alternative technologies for efficient computing. I am continuously working towards designing full stack solutions and template-based architectures for accelerating Machine Learning and Deep Learning algorithms on an FPGA. Besides my primary research-area of computer architecture, I have also worked at the intersection of machine learning, hardware design, programming languages and databases. In my free time, I like to spend time oil painting, cooking, and reading novels.


Accelerator-Based, Application-Specific and Reconfigurable Architecture, Architecture For Emerging Technologies and Applications, Iot, Mobile and Embedded Architecture
Picture of Devashree Tripathy

Devashree Tripathy

Graduate Student Researcher
University Of California, Riverside
Personal URL

Research Statement

I am a PhD candidate in the Department of Computer Science & Engineering at the University of California, Riverside. I work with Distinguished Prof. Laxmi Narayan Bhuyan and Prof.Daniel Wong and am a member of SoCal Lab at UCR. My interest lies in Computer Architecture , GPGPU Architecture design, High Performance Computing, Fault-Tolerance systems. I have worked on multiple projects on Data- Dependent Applications on GPGPU, Low power Design of GPGPU Execution units and have achieved notable improvements in terms of Performance gain and Power and Area saving.


Instruction, Thread and Data-Level Parallelism, Iot, Mobile and Embedded Architecture, Multiprocessor Systems
Picture of Khushboo


Post Doctoral Fellow
University of Florida, Indian Institute of Technology Guwahati
Personal URL

Research Statement

Thesis Title: LongLiveNoC: Wear Levelling, Write Reduction and Selective VC allocation for Long lasting Dark Silicon aware NoC Interconnects

Increasing processing demand has led to the development of chip multiprocessors which can have multiple to many cores connected with each other and with the on-chip caches. These connections are established by an on-chip packet-switched Network-on-Chip (NoC). Scaling of technology nodes increases the power dissipated by the chips leading to thermal restrictions. To control the chip thermal design power, certain components (like cores and caches) may be turned off. However, in this scenario of dark silicon, the interconnect is expected to be available.

The thesis aims to save power consumed by this always ON interconnect by replacing the power-hungry SRAM buffers in the routers with low leakage Non-Volatile Memory (NVM) based buffers. However, the major challenges with the employment of the NVMs are slower writes and weak write endurance.

The thesis proposes:
1. Methods to evenly distribute the writes across these NVM buffers in order to increase their lifetime. This is done by static and dynamic allocation of buffers to the virtual channels and their selection during packet transmission.

2. Power can also be saved by using frequency scaling of the routers and/or turning off certain buffers when the usage is less. The investigation is done for all such approaches and power savings are demonstrated.

3. Endurance can be improved and energy can be saved if we can reduce the number of writes performed on the buffers. This is achieved by proposing two compression techniques leading to reduced network traffic and improved lifetime.

All the above methods help in improving the lifetime of the NVM based NoC interconnects in the context of dark silicon.


Architecture For Emerging Technologies and Applications, Interconnection Network, Router and Network Interface Architecture, Multiprocessor Systems, Processor, Memory, and Storage Systems Architecture
Picture of Khyati


IIT Roorkee
Personal URL

Research Statement


Accelerator-Based, Application-Specific and Reconfigurable Architecture, Architecture For Emerging Technologies and Applications, Effects Of Circuits Or Technology On Architecture, Evaluation and Measurement Of Real Systems, Iot, Mobile and Embedded Architecture, Processor, Memory, and Storage Systems Architecture
We regularly organize a social gathering of women at the start of major architecture conferences (ISCA, HPCA, ASPLOS and MICRO).  These meet ups help newcomers to our conferences become better integrated in the community and reduce some of the pressure and intimidation they might feel at their first conference.  They provide great networking opportunities.  We hope to see you at the next one!
Would you like to attend a SIGARCH-sponsored event, but cannot because the cost of child-care is prohibitive? SIGARCH provides funds for a limited number of grants that support child care for members that would like to participate in a SIGARCH-sponsored event but are unable to do so without this support. SIGARCH provides financial assistance to subsidize a variety of child-care options. View details here.
Annually, we provide a brochure of upcoming female graduates in computer architecture. The goal of this brochure is to bring greater visibility to women on the job market and to celebrate their success as PhD students.

2018-2019 Candidates
2019 Candidates

Check out our WICARCH YouTube channel which features recorded technical talks by members of the WICARCH community.


We organize various initiatives to better connect women in computer architecture.


Applications are now open for 2022 Rising Stars in EECS workshops to be hosted by @utexasece and @UTCompSci at @UTAustin on Oct. 27-28. Apply now! at http://risingstars.utexas.edu #WhatStartsHere #TexasEngineering #TexasComputerScience #RisingStarsEECS

First session is tomorrow! 🙌🏼

Be sure to register for each of the three sessions currently announced, and sign on for the Google Form to stay in the loop about future ones! (Links in article.) https://twitter.com/sigarch/status/1400874243953463297

**New Deadline: March 29 11:59pm ET**

You can still quantum at @ISCAConfOrg!

Submit to I2Q, organized by members of @EPiQCExpedition / @UChicagoCS!

Website: https://epiqc.cs.uchicago.edu/workshop-i2q

@sigarch blogpost: https://sigarch.org/stairway-to-quantum/

#i2q #QuantumComputing #quantum #isca2021 #isca21

Join Our Mailing List

Our mailing list is maintained through ACM.  You can join in 3 easy steps:

1. Join SIGARCH/SIGMICRO (you don’t need to be a full ACM member — you can join a SIG only which is pretty cheap!)


2. Update your gender in your myACM account (create/activate account as needed)

Student members: if you log into myACM, you should see a “My Student Profile” on the left menu.  This is where you can specify gender.
Professional members: if you log into myACM, you should see a “My Professional and Technical Interest Profile” on the left menu you.  This is where you can specify gender.
3. Accept to receive emails from ACM:
In myACM, under “My Contact Information”, “Email Policy”, “Current preference” should have the box “Please send me ACM Announcements via email” checked.

Join Our Slack Channel

We offer an informal mentoring program through our slack channel (wicarch.slack.com).  Women at all career stages are encouraged to join.  The mentoring program provides an easy way to connect with other women and receive advice on a wide range of career and personal issues.

If you need assistance in joining our mailing list or slack channel, please send email to wicarch-chair@acm.org.

This website serves women in the field of computer architecture.
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