Call for Papers: NVMSA 2016

Submitted by Onur Mutlu
https://sites.google.com/a/camelab.org/nvmsa-2016/
April 1, 2016

Submitted by Onur Mutlu
https://sites.google.com/a/camelab.org/nvmsa-2016/

The 4th IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA)
Daegu, Korea
August 17-19, 2016
 

IMPORTANT DATES:
April 1: Abstract Submission Deadline
April 14: Paper Submission Deadline
June 1: Acceptance notification
June 12: Camera ready
 

Non-Volatile memory (NVM) technologies have demonstrated great potential to
improve many aspects of present and future memory hierarchies, offering high
integration density, larger capacity, zero standby power and good resilience
to soft errors. The recent research progress of various NVMs, e.g., NAND
flash, PCM, STT-RAM, RRAM, FeRAM, etc., have drawn tremendous attentions from
both academia and industry. Besides developing robust and scalable devices,
the unique characteristics of these NVM technologies, such as read-write
asymmetry, stochastic programming behavior, performance-power-nonvolatility
tradeoff, etc., introduce plenty of opportunities and challenges for novel
circuit designs, architectures, system organizations, and management
strategies. There is an urgent need for technology invention, modeling,
analysis, design and application of these NVMs ranging from circuit design to
system design levels.

IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA) provides a
fantastic opportunity for global nonvolatile memory researchers from different
communities to discuss and exchange knowledge, ideas, and insights, and to
facilitate the establishment of potential collaborations that can speed up the
progress in the design and application of NVMs. An expanded technical program
will be offered in NVMSA 2016 for the audience from academy and industry. The
organizing committee is soliciting papers on various topics related to NVMs
including (but not limited to):

Device/Circuit design of NVMs
– Emerging Non-volatile Memory Circuit Design
– NVM Device Design
– Error correction for NVMs
– Nonvolatile Logic Circuit Design

NVM Architectures and Systems
– Non-volatile Registers
– Non-volatile Memory Architectures
– Non-volatile Cache Design
– NVM-based Neuromorphic Architectures
– NVM-based Storage

NVM Software
– Operating System Support for NVM
– Compiler Optimization for NVM
– NVM-based File Systems
– NVM-based Storage Software
– NVM-based Databases
– NVM Controller Design

NVM Applications
– In-memory Computing
– NVM for Big Data Analytics
– NVM in Mobile Healthcare Applications
– NVM in Wearable Applications
– NVM and the Internet of Things

The topics of NVMSA cover the research and development advances in both
mainstream and emerging NVMs. The event is designed to foster interaction and
presentation of early results, new ideas and speculative directions. Thus,
NVMSA will combine the presentations of the papers accepted from the regular
submissions as well as a number of invited talks from researchers in academia,
technologists from industry, and case studies on the use of NVMs.
Participating authors are invited to submit six-page manuscripts to the
conference. All accepted papers will be published in the conference
proceedings. Conference content will be submitted for inclusion into IEEE
Xplore as well as other Abstracting and Indexing (A&I) databases.
Extensions of some selected papers will be published in a special issue of The
Journal of Systems Architecture: Embedded Software Design.

Associated Conference: The 22nd IEEE International Conference on
Embedded and Real-Time Computing Systems and Applications (RTCSA 2016)

Call for Papers: IEEE Micro General Interest 2016

Submitted by jayvant anantpur
https://sites.google.com/site/ieeemicro/call-for-papers/2016-cfp—general-interest-papers

Submitted by jayvant anantpur
https://sites.google.com/site/ieeemicro/call-for-papers/2016-cfp—general-interest-papers

IEEE Micro General Interest 2016

IEEE Micro seeks general-interest submissions for publication in upcoming 2016
issues. The submissions should present the design, performance, or application
of microcomputer and microprocessor systems. Summaries of work in progress
and descriptions of recently completed work are most welcome, as are tutorials
and position statements.

IEEE Micro is a bimonthly magazine of the IEEE Computer Society that reaches
an international audience of computer designers, system integrators, and users.
IEEE Micro publishes 6 to 8-page papers that are slightly less technical and
less quantitative than top-conference and archival journal papers, while being
insightful, slightly more qualitative, with a high tutorial value, and up to
date with current trends. IEEE Micro attracts a broad readership among both
academics and practitioners who want to keep up with new results and trends in
the field of computer architecture.

Areas of interest include, but are not limited to:
– Processor, memory, and storage systems architecture
– Parallel and multicore systems
– Data-center scale computing
– Architectures for handheld and mobile devices
– Application-specific, reconfigurable, or embedded architectures
– Heterogeneous and accelerator-based architectures
– Neuromorphic computing architectures
– Architectures for security and virtualization
– Power and energy efficient architectures
– Interconnection networks
– Instruction, thread, and data-level parallelism
– Dependable architectures
– Architectural support for programming productivity
– Network processor and router architectures
– Architectures for emerging technologies and applications
– Effect of circuits and technology on architecture
– Architecture modeling and simulation methodology
– Performance evaluation and measurement of real systems
– Design of high-performance and low-power chips

SUBMISSION PROCEDURE:
Log onto IEEE CS Manuscript Central (https://mc.manuscriptcentral.com/micro-cs)
and submit your manuscript. Please direct questions to the IEEE Micro magazine
assistant (micro-­ma@computer.org) regarding the submission site. For the
manuscript submission, acceptable file formats include Microsoft Word and PDF.
Manuscripts should not exceed 5,000 words including references, with each
average­ size figure counting as 250 words and each average-size table counting
as 150 words toward this limit. Please include all figures and tables, as well
as a cover page with author contact information (name, postal address, phone,
fax, and e­mail address) and a 200­-word abstract. Submitted manuscripts must
not have been previously published or currently submitted for publication
elsewhere, and all manuscripts must be cleared for publication. All previously
published papers must have at least 30% new content compared to any
conference (or other) publication. Accepted articles will be edited for
structure, style, clarity, and readability. For more information, please visit the
IEEE Micro Author Center (http://www2.computer.org/portal/web/peerreviewmagazines/acmicro).

The submission site is continuously open. Papers of general interest appear in
upcoming issues as space allows, or are grouped in the Nov/Dec 2016 issue.

Questions?
Contact the Editor-in-Chief, Lieven Eeckhout, at lieven.eeckhout@ugent.be

Call for papers: WDDD 2016

Submitted by Karu Sankaralingam
https://sites.google.com/site/iscawddd/
June 19, 2016

Submitted by Karu Sankaralingam
https://sites.google.com/site/iscawddd/
12th Annual Workshop on Duplicating, Deconstructing and Debunking

12th Annual Workshop on Duplicating, Deconstructing and Debunking (WDDD)
Seoul, S. Korea
June 19, 2016
 

IMPORTANT DATES:
Abstract Submission: April 20, 2016
Paper Submission: April 22, 2016
Acceptance: May 14, 2016
Final Version: June 10, 2016
 

WDDD provides the computer systems research community a forum for work that
validates or duplicates earlier results; deconstructs prior findings by
providing greater, in-depth insight into causal relationships or correlations;
or debunks earlier findings by describing precisely how and why proposed
techniques fail where earlier successes were claimed, or succeed where failure
was reported.

Traditionally, computer systems research conferences have focused almost
exclusively on novelty and performance, neglecting an abundance of interesting
work that lacks one or both of these attributes. A significant part of
research–in fact, the backbone of the scientific method–involves independent
validation of existing work and the exploration of strange ideas that never
pan out. This workshop provides a venue for disseminating such work in our
community. Published validation experiments strengthen existing work, while
thorough comparisons provide new dimensions and perspectives. Studies that
refute or correct existing work also strengthen the research community, by
ensuring that published material is technically correct and has sound
assumptions. Publishing negative or strange or unexpected results will allow
future researchers to learn the hard lessons of others, without repeating
their effort.

This workshop will set a high scientific standard for such experiments, and
will require insightful analysis to justify all conclusions. The workshop will
favor submissions that provide meaningful insights, and identify underlying
root causes for the failure or success of the investigated technique.
Acceptable work must thoroughly investigate and communicate why the proposed
technique performs as the results indicate. WDDD has a unique tradition of
asking the original paper authors to provide a follow-up comment after the
WDDD paper has been presented, where appropriate. The follow-up comment may
take the form of a rebuttal or additional insight from the original authors.

WORKSHOP SCOPE:
In general, any topic that is of interest to computer architecture conferences
and related systems areas are of potential interest for WDDD, so long as the
paper is in the spirit of the themes of Duplication, Deconstruction, and/or
Debunking.

Topics of interest:
– Independent validation of earlier results with meaningful analysis
– In-depth analysis and sensitivity studies that provide further insight into
earlier findings, or identify key parameters or assumptions that affect the
results
– Studies that refute earlier findings, with clear justification and explanation
– Negative results for ideas that intuitively make sense and should work, along
with explanations for why they do not
– Validation/refutation of controversial advertising claims by industrial
competitors

SUBMISSION GUIDELINES:
Submit a manuscript of up to 10 pages in two-column format by April 22, 2016
using the submission website. https://easychair.org/conferences/?conf=wddd16

ORGANIZERS:
Murali Annavaram, USC
Karu Sankaralingam, University of Wisconsin – Madison
David Brooks, Harvard University
Gabriel Loh, AMD Research

Call for Participation: SELSE 2016

Submitted by William H. Robinson
http://www.selse.org
March 29 to March 30, 2016

Submitted by William H. Robinson
http://www.selse.org

The 12th IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE 2016)
Austin, TX, USA
March 29 – 30, 2016
 

Early registration deadline: March 14th, 2016.

Keynote speakers:
SELSE 2016 will feature three keynote speeches by experts from
academia and industry.
– Dr. Krishna V. Palem, Rice University
Can the end of Moore’s Law result in new opportunities for computing?
– Dr. Nirmal Saxena, NVIDIA
Autonomous car is the new driver for resilient computing and
design-for-test.
– Dr. Martin Roetteler from Microsoft Research
Quantum error correction and quantum algorithmic discovery

Panel Discussion:
We will have a very interesting panel on the topic of approximate computing
with experts from academia and industry. The panel discussion will explore
opportunities and challenges of approximate computing in the field of
reliability.

Accommodations:
Please do not forget to book your hotels early, as the hotel prices can
increase closer to the SELSE dates. You can find a list of nearby hotels
on the SELSE web page.

Travel grants:
We are very excited to offer, for the first time, travel grants to young
faculties, postdocs, and students. Please refer to SELSE web page for
application instructions. Submit your application by March 12th.

ORGANIZERS:
General Chairs:
Helia Naeimi, Intel
Dan Alexandrescu, iRoC

Program Chairs:
Sudhanva Gurumurthi, IBM/University of Virginia
Mattan Erez, The University of Texas at Austin

Finance Chairs:
Siva Hari, NVIDIA
Daniel Lowell, AMD

Publicity Chairs:
William H. Robinson, Vanderbilt University
Paolo Rech, UFRGS
Yiannakis Sazeides, University of Cyprus

Documents Chairs:
Mehdi Tahoori, Karlsruhe Institute of Technology
Mojtaba Ebrahimi, Karlsruhe Institute of Technology

Austin Industry Liaison:
Indrani Paul, AMD

Webmaster:
Marios Kleanthous, Mesoyios College

Local Arrangements Chair:
Vijay Janapa Reddi, The University of Texas at Austin

Advisors to the Committee:
Sarah Michalak, LANL
Alan Wood, Oracle
Vilas Sridharan, AMD
Adrian Evans, iRoC

Call for Participation: OpenPiton Tutorial

Submitted by David Wentzlaff
http://parallel.princeton.edu/openpiton/ISCA16_tutorial.html

Submitted by David Wentzlaff
http://parallel.princeton.edu/openpiton/ISCA16_tutorial.html

OpenPiton Tutorial
co-located with ISCA 2016
Seoul, S. Korea
June 19, 2016
 

This tutorial will introduce the user to OpenPiton including how to use the
framework to build different designs. The tutorial will introduce the
verification framework (Verilog simulation), how to synthesize an OpenPiton
processor for a Xilinx FPGA board, it will demonstrate booting Linux on an
FPGA version of OpenPiton, it will familiarize users with how to use the
OpenPiton framework to target an ASIC tapeout, and it will show users how to
configure and extend the OpenPiton architecture to enable architecture
research. This tutorial will be hands-on so please bring a laptop.

OpenPiton is an open source framework designed to enable scalable architecture
research prototypes from 1 core to 500 million cores. OpenPiton is the
world’s first open source, general-purpose, multithreaded manycore processor
and framework. OpenPiton leverages the industry hardened OpenSPARC T1 core
with modifications and builds upon it with a scratch-built, scalable uncore
creating a flexible, modern manycore design. In addition, OpenPiton provides
synthesis and backend scripts for ASIC and FPGA to enable other researchers to
bring their designs to implementation. On FPGA, OpenPiton provides a new high
performance memory controller. OpenPiton provides a complete verification
infrastructure of over 8000 tests, is supported by mature software tools, runs
full-stack multiuser Debian Linux, and is written in industry standard
Verilog. Multiple implementations of OpenPiton have been created including a
taped-out 25-core implementation in IBM’s 32nm process and multiple Xilinx
FPGA prototypes.

Call for Papers: ASBD 2016

Submitted by xiufeng Sui
http://acs.ict.ac.cn/asbd2016/
June 19, 2016

Submitted by xiufeng Sui
http://acs.ict.ac.cn/asbd2016/

Sixth Workshop on Architectures and Systems for Big Data(ASBD 2016)
in conjunction with ISCA 2016
Seoul, S. Korea
June 18, 2016
 

IMPORTANT DATES:
Submissions deadline: April 10, 2016
Author notification: April 30, 2016
 

The term “Big Data” refers to the continuing massive expansion in the data
volume and diversity as well as the speed and complexity of data processing.
The use of big data underpins critical activities in all sectors of our
society. Achieving the full transformative potential of big data in this
increasingly digital world requires both new data analysis algorithms and
a new class of systems to handle the dramatic data growth, the demand to
integrate structured and unstructured data analytics, and the increasing
computing needs of massive-scale analytics.

We are pleased to request papers for presentation at the upcoming Sixth
Workshop on Architectures and Systems for Big Data (ASBD 2016) held in
conjunction with ISCA-43. The workshop will provide a forum to exchange
research ideas related to all critical aspects of emerging analytics systems
for big data, including architectural support, benchmarks and metrics, data
management software, operating systems, and emerging challenges and
opportunities. We hope to attract a group of interdisciplinary researchers
from academia, industry and government research labs. To encourage
discussion between participants, the workshop will include significant time
for interactions between the presenters and the audience. We also plan to
have a keynote speaker and/or panel session.

Topics of interest include but are not limited to:
– Processor, memory and system architectures for data analytics
– Benchmarks, metrics and workload characterization for big data
– Accelerators for analytics and data-intensive computing
– Implications of data analytics to mobile and embedded systems
– Energy efficiency and energy-efficient designs for analytics
– Availability, fault tolerance and data recovery in big data environments
– Scalable system & network designs for high concurrency/bandwidth streaming
– Data management and analytics for vast amounts of unstructured data
– Evaluation tools, methodologies and workload synthesis
– OS, distributed systems and system management support for large-scale
analytics
– Debugging and performance analysis tools for analytics and big data
– Programming systems and language support for deep analytics
– MapReduce and other processing paradigms for analytics

We encourage researchers from all institutions to submit their work for review.
Preliminary results of interesting ideas and work-in-progress are welcome.
Submissions that are likely to generate vigorous discussion will be favored!

SUBMISSION GUIDELINES:
All papers should be submitted in PDF format, using 10 point
or larger font for text (8 points or larger for figures and tables),
total length not to exceed 6 pages.
Submission site: https://easychair.org/conferences/?conf=asbd2016

ORGANIZERS:
Workshop Co-Organizers:
Lixin Zhang, ICT/CAS China
Yungang Bao, ICT/CAS China

Program Co-Chairs:
John Kim, KAIST South Korea
Xiufeng Sui, ICT/CAS China

Program Committee:
TBD

Steering Committee:
Jian Li, Huawei
Jichuan Chang, Google
Evan Speight, IBM Research

Call for Nominations: The Rau Award 2016

Submitted by Milagros Lovos
https://www.computer.org/web/awards/rau
February 26, 2016 at 08:00

Submitted by Milagros Lovos
https://www.computer.org/web/awards/rau

The Rau Award

Established in memory of Dr. B. (Bob) Ramakrishna Rau, the award recognizes his
distinguished career in promoting and expanding the use of innovative computer
microarchitecture techniques, including his innovation in compiler technology,
his leadership in academic and industrial computer architecture, and his
extremely high personal and ethical standards.

WHO IS ELIGIBLE?
The candidate will have made an outstanding, innovative contribution or
contributions to microarchitecture, use of novel microarchitectural techniques
or compiler/architecture interfacing. It is hoped, but not required, that the
winner will have also contributed to the computer microarchitecture
community through teaching, mentoring, or community service.

AWARD:
Certificate and a $2,000 honorarium.

PRESENTATION:
This year’s award will be presented at the ACM/IEEE International Symposium
on Microarchitecture (MICRO-49), held in October 15-19, 2016 in Taipei Taiwan.

NOMINATION SUBMISSION:
This award requires 3 endorsements.
Nominations are being accepted electronically through http://www.computer.org/web/awards/rau

PAST RECIPIENT:
Robert P. Colwell – “For contributions to critical analysis of microarchitecture and
the development of the Pentium Pro processor.”

IEEE Computer Society Awards site: www.computer.org/awards
IEEE Computer Society Award Nominations site: http://awards.computer.org/

Available Now: Datacenter Design and Management (Book)

Submitted by Brent Beckley
http://www.morganclaypoolpublishers.com/catalog_Orig/product_info.php?products_id=910

Submitted by Brent Beckley
http://www.morganclaypoolpublishers.com/catalog_Orig/product_info.php?products_id=910

Datacenter Design and Management

An era of big data demands datacenters, which house the computing
infrastructure that translates raw data into valuable information. This book
defines datacenters broadly, as large distributed systems that perform
parallel computation for diverse users. These systems exist in multiple forms
(private and public) and are built at multiple scales. Datacenter design and
management is multifaceted, requiring the simultaneous pursuit of multiple
objectives. Performance, efficiency, and fairness are first-order design and
management objectives, which can each be viewed from several perspectives.
This book surveys datacenter research from a computer architect’s perspective,
addressing challenges in applications, design, management, server simulation,
and system simulation.

Call For Submissions: Championship Branch Prediction Competition

Submitted by Ronald Dreslinski
http://www.jilp.org/cbp2016/

Submitted by Ronald Dreslinski
http://www.jilp.org/cbp2016/

Championship Branch Prediction Competition
co-located with ISCA 2016
Seoul, South Korea
June 19, 2016
 

The workshop on computer architecture competitions is a forum for holding
competitions to evaluate computer architecture research topics. The fifth
JWAC workshop is organized around a competition for branch prediction
algorithms. The Championship Branch Prediction (CBP) invites contestants
to submit their branch prediction code to participate in this competition.
Contestants will be given a fixed storage budget to implement their best
predictors on a common evaluation framework provided by the organizing
committee. Please see the website for more information.

Submissions Due: May 6, 2016.

Call for Participation: ASPLOS 2016

Submitted by Changhee Jung
https://www.ece.cmu.edu/calcm/asplos2016/
April 2 to April 6, 2016

Submitted by Changhee Jung
https://www.ece.cmu.edu/calcm/asplos2016/

The Twenty First International Conference on Architectural Support
for Programming Languages and Operating Systems (ASPLOS 2016)

Atlanta, Georgia, USA
April 2-6, 2016
 

– Travel Grant Application Deadline: March 1:
https://www.ece.cmu.edu/calcm/asplos2016/grants.html

– Hotel Registration Deadline: March 11:
https://www.ece.cmu.edu/calcm/asplos2016/hotel.html

– Conference Early Registration Deadline: March 11:
https://www.regonline.com/Register/Checkin.aspx?EventID=1807654&