Call For Papers: ISPASS 2017

The IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
San Francisco Bay Area, California, USA
April 23-25, 2017

Paper abstract submission: October 7, 2016
Full submission: October 14, 2016
Rebuttal: January 13-16, 2017
Notification: January 30, 2017
Conference: April 23-25, 2017

The IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) provides a forum for sharing advanced academic and industrial research work focused on performance analysis in the design of computer systems and software. Authors are invited to submit previously unpublished work for possible presentation at the conference. Papers are solicited in fields that include the following:

Performance and power evaluation methodologies
– Analytical modeling
– Statistical approaches
– Tracing and profiling tools
– Simulation techniques
– Hardware (e.g., FPGA) accelerated simulation
– Hardware performance counter architectures
– Power/Temperature/Variability/Reliability models for computer systems
– Microbenchmark-based hardware analysis techniques
Performance and power analysis
– Metrics
– Bottleneck identification and analysis
– Visualization
Power/Performance analysis of commercial and experimental hardware
– General-purpose microprocessors
– Multithreaded, multicore and many-core architectures
– Accelerators and graphics processing units
– Memory systems including storage class memory
– Embedded and mobile systems
– Enterprise systems and data centers
– Supercomputers
– Computer networks
Power/Performance analysis of emerging workloads and software
– Software written in managed languages
– Virtualization and consolidation workloads
– Internet-sector workloads
– Embedded, multimedia, games, telepresence
– Bioinformatics, life sciences, security, biometrics
– Deep learning and convolutional neural networks
Application and system code tuning and optimization
Confirmations or refutations of important prior results

In addition to research papers, ISPASS welcomes tools and benchmarks papers. The conference is an ideal forum to publicize new tools and benchmarks to the community. These papers, which can detail tools and benchmarks in any of the above fields of interest, will be judged primarily on their potential impact and use than on their research contribution.

See the conference web site for submission details.

General Chair:
Suzanne Rivoire, Sonoma State University

Program Committee Chair:
Bronis R. de Supinski, LLNL

Program Committee:
Dorian Arnold, University of New Mexico
Laura Carrington, San Diego Supercomputing Center
Almadena Chtchelkanova, NSF
Marcelo Cintra, Intel
Jeanine Cook, Sandia National Laboratories
Luiz DeRose, Cray
Christina Delimitrou, Cornell University
Andi Drebes, The University of Manchester
Lieven Eeckhout, Ghent University
Wendy Elsasser, ARM
Nikos Hardavellas, Northwestern University
David Hass, Broadcom
Hillery Hunter, IBM Research
Katherine Isaacs, University of Arizona
Lizy John, University of Texas
Samira Khan, University of Virginia
Masaaki Kondo, The University of Tokyo
David Lowenthal, University of Arizona
Xiaosong Ma, Qatar Computing Research Institute
Naoya Maruyama, RIKEN AICS
Dimitrios Nikolopoulos, Queen’s University, Belfast
Tapasya Patki, LLNL
Indrani Paul, AMD
Michael Pellauer, NVIDIA
Fabrizio Petrini, Intel
Suzanne Rivoire, Sonoma State University
Valentina Salapura, IBM Research
Yanos Sazeides, University of Cyprus
Thomas Scogland, LLNL
Kelly Shaw, University of Richmond
Estela Suarez, Jülich Supercomputing Centre
Linglia Tang, University of Michigan
Michela Taufer, University of Delaware
Valerie Taylor, Texas A&M University
Eric Van Hensbergen, ARM
Jeffrey S. Vetter, Oak Ridge National Laboratory
Vince Weaver, University of Maine
Thomas F. Wenisch, University of Michigan

Call for Papers: Workshop on Irregular Applications: Architectures and Algorithms

IA^3 2016 – Sixth Workshop on Irregular Applications: Architectures and Algorithms
in conjunction with SC16 and SIGHPC
Salt Lake City, UT
November 13, 2016

Abstract submission: August 23, 2016
Position or full paper submission: August 29, 2016
Notification of acceptance: October 3, 2016
Camera-ready position and full papers: October 10, 2016
Workshop: November 13, 2016

Irregular applications occur in many subject matters. While inherently parallel, they exhibit highly variable execution performance at a local level due to unpredictable memory access patterns and/or network transfers, divergent control structures, and data imbalances. Moreover, they often require fine-grain synchronization and communication on large-data structures such as graphs, trees, unstructured grids, tables, sparse matrices, deep nets, and their combinations (such as, for example, attributed graphs). They have a significant degree of latent parallelism, which however is difficult to exploit due to their complex behavior. Current high performance architectures rely on data locality and regular computation to reduce access latencies, and often do not cope well with the requirements of these applications. Furthermore, irregular applications are difficult to scale on current supercomputing machines, due to their limits in fine-grained synchronization and small data transfers.

Irregular applications pertain both to well established and emerging fields, such as machine learning, social network analysis, bioinformatics, semantic graph databases, Computer Aided Design (CAD), and computer security. Many of these application areas also process massive sets of unstructured data, which keep growing exponentially. Addressing the issues of irregular applications on current and future architectures will become critical to solve the challenges in science and data analysis of the next few years.

This workshop seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system-architecture, network, languages and libraries, runtimes, compilers, analysis, algorithms. Topics of interest, of both theoretical and practical significance, include but are not limited to:

– Micro- and System-architectures, including multi- and many-core designs, heterogeneous processors, accelerators (GPUs, vector processors, Automata processor), reconfigurable (coarse grained reconfigurable and FPGA designs) and custom processors
– Network architectures and interconnect (including high-radix networks, optical interconnects)
– Novel memory architectures and designs (including processors-in memory)
– Impact of new computing paradigms on irregular workloads (including neuromorphic processors and quantum computing)
– Modeling, simulation and evaluation of novel architectures with irregular workloads
– Innovative algorithmic techniques
– Combinatorial algorithms (graph algorithms, sparse linear algebra, etc.)
– Impact of irregularity on machine learning approaches
– Parallelization techniques and data structures for irregular workloads
– Data structures combining regular and irregular computations (e.g., attributed graphs)
– Approaches for managing massive unstructured datasets (including streaming data)
– Languages and programming models for irregular workloads
– Library and runtime support for irregular workloads
– Compiler and analysis techniques for irregular workloads
– High performance data analytics applications, including graph databases

Besides regular papers, papers describing work-in-progress or incomplete but sound, innovative ideas related to the workshop theme are also encouraged. We solicit both 8-page regular papers and 4-page position papers. Authors of exciting but not mature enough regular papers may be offered the option of a short 4-page paper and related short presentation.

All submissions should be in double-column, single-spaced letter format, using 10-point size fonts, with at least one-inch margins on each side, and respect the IEEE conference templates available at
Submission site:

The proceedings of the workshop will be published in cooperation with ACM SIGHPC and available from the ACM Digital Library.

Submitted manuscripts may not exceed 8 pages in length for regular papers and 4 pages for position papers including figures, tables and references.

Antonino Tumeo, PNNL
John Feo, PNNL, Northwest Institute for Advanced Computing (NIAC)
Oreste Villa, NVIDIA Research

Program Committee:
Scott Beamer, Lawrence Berkeley National Laboratory, US
Michela Becchi, University of Missouri, US
David Brooks, Harvard University, US
Hubertus Franke, IBM TJ Watson, US
John Gilbert, University of California at Santa Barbara, US
Maya Gokhale, Lawrence Livermore National Laboratory, US
Vivek Kumar, Rice University, US
John Leidel, Texas Tech University, US
Kamesh Madduri, Penn State University, US
Naoya Maruyama, RIKEN AICS, JP
Satoshi Matsuoka, Tokio Institute of Technology, JP
Tim Mattson, Intel, US
Richard Murphy, Micron, US
Miquel Moretó, UPC-BSC, ES
Walid Najjar, University of California Riverside, US
Jacob Nelson, University of Washington, US
Ozcan Ozturk, Bilkent University, TR
Gianluca Palermo, Politecnico di Milano, IT
D.K. Panda, The Ohio State University, US
Fabrizio Petrini, Intel, US
Jason Riedy, Georgia Institute of Technology, US
Daniel Sanchez, Massachusetts Institute of Technology, US
Erik Saule, University of North Carolina at Charlotte, US
John Shalf, Lawrence Berkeley National Laboratory, US
Ruud Van Der Pas, Oracle, US
Flavio Vella, Sapienza, University of Rome, IT

Call for Papers: International Symposium on Hardware Oriented Security and Trust

IEEE International Symposium on Hardware Oriented Security and Trust (HOST 2017)
McLean, Virginia, USA
May 3-5, 2016

Abstract Deadline: November 1, 2016
Paper Submission Deadline: November 8, 2016
Notification of Acceptance: January 31, 2017
Camera-ready Version: February 28, 2017
Hardware Demo Proposal: March 15, 2017

IEEE International Symposium on Hardware Oriented Security and Trust (HOST) aims to facilitate the rapid growth of hardware-based security research and development. HOST highlights new results in the area of hardware and system security. Relevant research topics include techniques, tools, design/test methods, architectures, circuits, and applications of secure hardware.

HOST 2017 invites original contributions related to, but not limited by, the following topics:
– Hardware Trojan attacks and detection techniques
– Hardware techniques to facilitate software and/or system security
– Hardware-based security primitives (PUFs, RNGs)
– System-on-chip (SoC) security
– Side-channel attacks and protection
– Security, privacy, and trust protocols
– Metrics, policies, and standards related to hardware security
– Hardware IP trust (watermarking, metering, trust verification)
– Trusted manufacturing including split manufacturing and 3D ICs
– Security analysis and protection of Internet of Things (IoT)
– Secure and efficient implementation of crypto algorithms
– Reverse engineering and hardware obfuscation
– Supply chain risks mitigation (e.g., counterfeit detection & avoidance)
– Hardware tampering attacks and protection
– Applications of hardware security to secure system development

You can register and submit your paper at: The page limit is 6 pages, double column, IEEE format, with a minimum font size of 10 points. Submissions are anonymous and must not identify the authors, directly or indirectly, anywhere in the manuscript.

Students can participate in a hardware demo session by submitting a 1-page proposal describing the research and features to be demonstrated on an FPGA or other hardware platform. Please upload your proposal to EasyChair by March 15, 2017.
A best paper award will be given to paper whose first author is a full-time student.
A best presentation award will be given to a speaker who is a full-time student.
Travel grants are available for graduate and undergraduate students.

General Chair:
William H. Robinson, Vanderbilt University

Program Chair:
Swarup Bhunia, University of Florida

Call for Participation: NOCS 2016

10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016)
August 31 – September 2, 2016
Nara, Japan

The International Symposium on Networks-on-Chip (NOCS) is the premier event dedicated to interdisciplinary research on on-chip, chip-scale, and multichip package scale communication technology, architecture, design methods, applications and systems. NOCS brings together scientists and engineers working on NoC innovations and applications from inter-related research communities, including computer architecture, networking, circuits and systems, packaging, embedded systems, and design automation.

NOCS 2016 will be held in Nara. It is well connected to Kyoto and Osaka. The nearest airport is Kansai International Airport, which is also well connected to many international cities. Nara was the capital of Japan about 1300 years ago. There are historical temples, shrine, palace, and forest encompassed as Historic Monuments of Ancient Nara.

Advanced program, registration, and hotel reservation are available online.

Keynote Talks:
– Near-Field Coupling Integration Technology. Tadahiro Kuroda (Keio University, Japan)
– Identifying On-Chip Communication Requirements for IOT. Rob Aitken (ARM Inc., USA)

Embedded Tutorial:
Inter/Intra-Chip Optical Interconnection Network: Opportunities, Challenges, and Implementations. Jiang Xu (Hong Kong University of Science and Technology, Hong Kong), Yuichi Nakamura (NEC Corp., Japan)

General Co-Chairs:
– Hideharu Amano (Keio University, Japan)
– Partha Pratim Pande (Washington State University, USA)

Technical Program Co-Chairs:
– Hiroki Matsutani (Keio University, Japan)
– Sriram Vangal (Intel, USA)

Call for Papers: CCGrid 2017

The 17th IEEE/ACM International Symposium On Cluster, Cloud And Grid Computing (CCGrid 2017)
Madrid, Spain
May 14-17

Papers due: November 16, 2016
Author notifications: January 15, 2017

Advances in architectures, networks, systems and middleware technologies are leading to new concepts and platforms for computing, ranging from Clusters and Grids to Clouds and Datacenters. CCGrid 2017 is a forum bringing together international researchers, developers, and practitioners to present leading research activities and results on a broad range of topics related to these concepts, platforms, and their applications. The conference features keynotes, technical presentations, workshops, and posters, as well as the Doctoral Symposium and the SCALE challenge featuring live demonstrations. In 2017, CCGrid will come to Spain and will be held in Madrid.

Topics of interest include, but are not limited to:
– Applications and Big Data
– Architecture and Networking
– Data Centers and CyberInfrastructure
– Programming Models and Runtime Systems
– Performance Modeling and Evaluation
– Scheduling and Resource Management
– Mobile and Hybrid Clouds
– Storage and I/O
– Security, Privacy and Reliability

Authors are invited to submit papers electronically in PDF format. Submitted manuscripts should be structured as technical papers and may not exceed 10 letter-size (8.5 x 11) pages including all figures, tables and references using the IEEE format for conference proceedings. For the final camera-ready version, authors with accepted papers may purchase up to two additional pages at the following rates: 100 USD for each page.

Submissions not conforming to these guidelines may be returned without review. The official language of the conference is English. All manuscripts will be reviewed and judged on technical strength, originality, significance, quality of presentation, and interest and relevance to the conference attendees.

The proceedings will be published through the IEEE Computer Society Conference Publishing Services. Submitted papers must represent original unpublished research that is not currently under review for any other conference or journal. Papers not following these guidelines will be rejected without review and further action may be taken, including (but not limited to) notifications sent to the heads of the institutions of the authors and sponsors of the conference. Submissions received after the due date, exceeding the page limit, or not appropriately structured may not be considered. Authors may contact the conference chairs for more information.

The paper submission online system is

General Chairs:
Jesús Carretero (University Carlos III of Madrid, Spain)
Manish Parashar (Rutgers University, USA)

Program Chairs:
Franck Cappello, (Argonne National Laboratory and University of Illinois at Urbana, USA) Geoffrey Charles Fox (Indiana University, USA)
Javier Garcia-Blas (University Carlos III of Madrid, Spain)

Honorary Chair:
Mateo Valero, Barcelona Supercomputing Center, Spain

Call for Workshops and Tutorials: CGO 2017

International Symposium on Code Generation and Optimization (CGO)
Austin, Texas, USA
February 4-8, 2017

Deadline for proposals: August 26, 2016

We’re seeking proposals for workshops and tutorials on Saturday and Sunday before the main conference. This is your event’s chance to take advantage of the interdisciplinary audience of CGO, HPCA, and PPoPP. Please submit a proposal!

Details on submission are on the CGO site:

Call for Submissions: SC16 Birds-of-a-Feather Sessions

ACM/IEEE International Conference for High Performance Computing, Networking, Storage, and Analysis (SC16)
Salt Lake City, Utah
Nov 13-18, 2016

Submission Deadline: July 31, 2016
Notification Sent: September 1, 2016

Engage in conversations that will ultimately improve our lives and our world! The Birds-of-a-Feather (BOF) sessions are among the most interactive, popular, and well-attended sessions of the SC Conference Series. The BOF sessions provide a non-commercial, dynamic venue for conference attendees to openly discuss current topics of focused mutual interest within the HPC community with a deep emphasis on audience-guided discussion, professional networking and grassroots participation.

SC16 will continue this tradition with a full schedule of exciting, informal, interactive sessions focused around a variety of special topics of mutual interest.

BOF sessions are an excellent opportunity to connect and interact with other attendees with whom you share a mutual interest. SC16 will feature BOF sessions covering a range of topics in the following areas: algorithms, applications, architectures and networks, clouds and distributed computing, data analytics, visualization and storage, education, outreach, performance measurement, modeling and tools, programming models and software systems, as well as the “state-of-the-practice”.


SC16 Birds-of-a-feather Chair:
Manish Parashar (Rutgers University)

SC16 Birds-of-a-feather Vice Chair:
Amy Apon (Clemson University)

Call for Papers: NoCArc 2016

9th International Workshop on Network on Chip Architectures
in conjunction with IEEE/ACM MICRO-49
October 15 or 16, 2016
Taipei, Taiwan

– Abstract submission deadline: July 25, 2016
– Paper submission deadline: August 1, 2016
– Acceptance notification: September 1, 2016
– Camera-ready version due: September 8, 2016

Current multicore architectures formed by tens of processing cores will be soon replaced by the next generation of manycore architectures with hundreds of cores. In fact, the International Technology Roadmap for Semiconductors foresees that the number of Processing Elements (PEs) that will be integrated into a System-on-Chip (SoC) will be in the order of thousand within the 2020. As the number of communicating elements increases, there is a need for an efficient, scalable and reliable communication infrastructure. As technology geometries shrink to the deep submicron regime, however, the communication delay and power consumption of global interconnections become the major bottleneck. The Network-on- Chip (NoC) design paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues such as performance limitations of long interconnects, and integration of large number of PEs on a chip.

The goal of NoCArc workshop is to provide a forum for researchers to present and discuss innovative ideas and solutions related to design and implementation of multi-core systems on chip. The workshop will focus on issues related to design, analysis and testing of on-chip networks.

The workshop will focus on issues related to design, analysis and testing of on-chip networks. The topics of specific interest for the workshop include, but are not limited to:

NoC Architecture and Implementation
– Topologies, routing, flow control
– Managing QoS
– Timing, synchronous/asynchronous communication
– Reliability issues
– Design methodologies and tools
– Signaling & circuit design for NoC links
– NoC Analysis and Verification

Power, energy and thermal issues
– Benchmarking and experience with NoC-based systems
– Modeling, simulation, and synthesis
– Verification, debug and test
– Metrics and benchmarks
– NoC Application

Mapping of applications onto NoCs
– NoC case studies, application-specific NoC design
– NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
– NoC designs for heterogeneous systems
– On-Chip Communication Optimization

Communication efficient algorithms
– Multi/many-core communication workload characterization and evaluation
– Energy efficient NoCs and energy minimization
– NoC at System-level

Design of memory subsystem
– NoC support for memory and cache access
– OS support for NoCs
– Programming models including shared memory, message passing and novel programming models
– Issues related to large-scale systems (datacenters, supercomputers) with NoC-based systems as building blocks

Emerging NoC Technologies
– Wireless, Optical, and RF
– NoCs for 3D and 2.5D packages

Besides regular papers, papers describing work in progress or incomplete but sound new innovative ideas related to the workshop theme are also encouraged.

Both research and application-oriented papers are welcome. All papers should be submitted electronically by EasyChair. Papers must be in PDF format and should include title, authors and affiliation, e-mail address of the contact author. Additional information at

General Co-Chairs
– Maurizio Palesi, Univ. of Enna, KORE, Italy
– Masoud Daneshtalab, Univ. of Turku, Finland and KTH, Sweden
– Xiaohang Wang, South China University of Technology, China

TPC Co-Chairs
– Masoumeh Ebrahimi, Univ. of Turku, Finland
– Davide Patti, Univ. of Catania, Italy

Call for Nominations: Seymour Cray, Sidney Fernbach & ACM/IEEE-CS Ken Kennedy Awards

Call for Nominations: Seymour Cray, Sidney Fernbach & ACM/IEEE-CS Ken Kennedy Awards
Award Presentation: SC16
Salt Lake City, Utah, USA
Nov 14-18, 2016

Nomination Deadline: July 1, 2016

Established in late 1997 in memory of Seymour Cray, the Seymour Cray Award is awarded to recognize innovative contributions to high performance computing systems best exemplify the creative spirit demonstrated by Seymour Cray. The award consists of a crystal memento and honorarium of $10,000. This award requires 3 endorsements.

Established in 1992 by the Board of Governors of the IEEE Computer Society. It honors the memory of the late Dr. Sidney Fernbach, one of the pioneers on the development and application of high performance computers for the solution of large computational problems. The award, which consists of a certificate and a $2,000 honorarium, is presented annually to an individual for “an outstanding contribution in the application of high performance computers using innovative approaches.” This award requires 3 endorsements.

Established in memory of Ken Kennedy, the founder of Rice University’s nationally ranked computer science program and one of the world’s foremost experts on high-performance computing. A certificate and $5,000 honorarium are awarded jointly by the ACM and the IEEE Computer Society for outstanding contributions to programmability or productivity in high- performance computing together with significant community service or mentoring contributions. This award requires 2 endorsements.

For nomination queries, please write to or visit

Call for Papers: HPCA 2017

23rd IEEE International Symposium on High-Performance Computer Architecture (HPCA)
collocated with CGO and PPoPP
Austin, Texas, USA
February 4 – 8, 2017

Abstract submission: July 25, 2016, 11:59 PM CDT
Paper submission: August 1, 2016, 11:59 PM CDT
Notification of paper outcome: October 12, 2016

The International Symposium on High-Performance Computer Architecture provides a high-quality forum for scientists and engineers to present their latest research findings in this rapidly-changing field. Authors are invited to submit papers on all aspects of high-performance computer architecture.

Topics of interest include, but are not limited to:
– Processor, cache, and memory architectures
– Parallel computer architectures
– Multicore and multiprocessor architectures
– Impact of technology on architecture
– Power-efficient architectures and techniques
– Dependable/secure architectures
– High-performance I/O systems
– Embedded, reconfigurable, and heterogeneous architectures
– Interconnect and network interface architectures
– Architectures for cloud-based HPC and data centers
– Innovative hardware/software trade-offs
– Impact of compilers and system software on architecture
– Performance modeling and evaluation
– Architectures for emerging technology and applications

Authors should submit an abstract by July 25, 2016 11:59 PM CDT. They should submit the full version of the paper August   1, 2016, 11:59 PM CDT. No extensions will be granted. The full version should be a PDF file following the submission guidelines that will be made available at the submission website.  Papers should be submitted for blind review. We anticipate making a Best Paper award; all papers will be evaluated based on their novelty, fundamental insights, experimental evaluation, and potential for long-term impact.  New-idea papers as well as papers that significantly advance established areas are strongly encouraged. Submission issues should be directed to the program chair at djimenez@cse.tamu. edu . Details formatting and submission guidelines will be made available at HPCA-23 will host an Industrial Paper Session presenting novel insights from industry. See the HPCA 2017 website for submission details.

Sponsored by the IEEE Computer Society TC on Computer Architecture

General Chair:
Derek Chiou, Microsoft and UT Austin

Program Chair:
Daniel A. Jimenez, Texas A&M University

Program Committee:
Valeria Bertacco, Michigan
Abhishek Bhattacharjee, Rutgers
Reetuparna Das, Michigan
Hadi Esmaeilzadeh, Georgia Tech
Yoav Etsion, Technion
Babak Falsafi, EPFL
Michael Ferdman, Stony Brook University
Antonio Gonzalez, UPC
Paul Gratz, Texas A&M
Nikos Hardavellas, Northwestern University
Kei Hiraki, University of Tokyo
Jaehyuk Huh, KAIST
Engin Ipek, Rochester
David Kaeli, Northeastern
Samira Khan, UVA
Hyesoon Kim, Georgia Tech
Tao Li, Florida and NSF
Calvin Lin, UT Austin
Gabriel H. Loh, AMD
Shih-Lien Lu, TSMC
Pierre Michaud, Inria
Timothy N. Miller, Binghamton University (SUNY)
Miquel Moreto, BSC and UPC
Andreas Moshovos, Toronto
Trevor Mudge, Michigan
Onur Mutlu, ETH Zurich and CMU
Abdullah Muzahid, UT San Antonio
Vijay Nagarajan, University of Edinburgh
Soner Onder, Michigan Tech
Yale N. Patt, UT Austin
Miquel Pericas, Chalmers University of Technology
Alex Ramirez, NVIDIA
Karu Sankaralingam, Wisconsin
Yan Solihin, NCSU and NSF
Yingying Tian, AMD
Mohit Tiwari, UT Austin
Josep Torrellas, UIUC
Thomas F. Wenisch, Michigan
David Wentzlaff, Princeton
Carole-Jean Wu, ASU
Yuan Xie, UCSB
Mohamed Zahran, NYU
Antonia Zhai, Minnesota
Lixin Zhang, Institute of Computing Technology, CAS
Huiyang Zhou, NCSU

Industrial Session Chair:
Chris Wilkerson, Intel Labs

Local Arrangements Chair:
Mohit Tiwari, UT Austin

Workshops and Tutorials Chair:
Mike Ferdman, Stony Brook University

Finance Chair:
Dam Sunwoo, ARM

Publications Chair:
Xuehai Qian, USC

Travel Awards Chair:
Zhenman Fang, UCLA

Publicity Chair:
Michael Papamichael, Microsoft Research

Web and Submissions Chairs:
Hung-Wei Tseng, UCSD and Elvira Teran, Texas A&M and Intel Labs

Industrial Session Chair:
Chris Wilkerson, Intel Labs

Local Arrangements Chair:
Mohit Tiwari, UT Austin

Workshops and Tutorials Chair:
Mike Ferdman, Stony Brook University

Finance Chair:
Dam Sunwoo, ARM

Publications Chair:
Xuehai Qian, USC

Travel Awards Chair:
Zhenman Fang, UCLA

Publicity Chair:
Michael Papamichael, Microsoft Research

Web and Submissions Chairs:
Hung-Wei Tseng, UCSD and Elvira Teran, Texas A&M and Intel Labs