Call for Participation: ASPLOS 2016

Submitted by Changhee Jung
April 2 to April 6, 2016

Submitted by Changhee Jung

The Twenty First International Conference on Architectural Support
for Programming Languages and Operating Systems (ASPLOS 2016)

Atlanta, Georgia, USA
April 2-6, 2016

– Travel Grant Application Deadline: March 1:

– Hotel Registration Deadline: March 11:

– Conference Early Registration Deadline: March 11:

Call for Papers: MEMSYS 2016

Submitted by Aamer Jaleel
March 18, 2016

Submitted by Aamer Jaleel

Memory Systems Conference (MEMSYS)
Washington, DC, USA

Submission Deadline: March 18*, 2016
Notification: May 15, 2016
Camera-Ready: July 1, 2016
* There will be an automatic submission extension of one week

The memory system has become extremely important recently: memory is slow,
and this is the primary reason that computers don’t run significantly faster than
they do. In large-scale computer installations such as the building-sized
systems powering,, and the financial sector, memory is
often the largest dollar cost as well as the largest consumer of energy.
Consequently, improvements in the memory system can have significant impact on
the real world, improving power and energy, performance, and/or dollar cost.

Moreover, many of the problems we see in the memory system are
cross-disciplinary in nature—their solution would likely require work at all
levels, from applications to circuits. Thus, while the scope of the problem is
memory, the scope of the solutions will be much wider.

Areas of Interest

Previously unpublished papers containing significant novel ideas and technical
results are solicited. Papers that focus on system, software, and architecture
level concepts, outside of traditional conference scopes, will be preferred
over others (e.g., the desired focus is away from pipeline design, processor
cache design, prefetching, data prediction, etc.). Symposium topics include,
but are not limited to, the following:

– Memory system design from both hardware & software perspectives
– Operating system design for hybrid/nonvolatile memories
– Technologies including PCM, flash, DRAM, STT-RAM, 3DXP, etc.
– Data-movement issues and mitigation techniques
– Interconnects to support large-scale data movement
– Software & application techniques for distributed memories
– Software management techniques
– Near-memory computing
– Memory-centric programming models & compiler techniques
– Memory failure modes and mitigation strategies
– Memory and system security issues

To reiterate, papers that focus on topics outside of traditional conference
scopes will be preferred over others.

Our primary goal is to showcase interesting ideas that will spark conversation
between disparate groups—to get applications people and operating systems
people and system architecture people and interconnect people and circuits
people to talk to each other. We accept extended abstracts, position papers,
and/or full research papers, and each accepted submission is given a 20-minute
presentation time slot. All accepted papers will be published in the ACM
Digital Library.

Submission formats:
2 page Extended Abstracts
5–6 page Position Papers
10–12 page Research Papers

Conference paper layout, no less than 9pt font in body, two-column, blind
submission, up to 15 pages in length.

All accepted submissions will be presented, published in the ACM Digital
Library, and included in the printed conference proceedings.

Note: Submitting either Extended Abstracts or Position Papers will not
preclude an author from submitting their work, in a longer research format,
to another publication forum at a later date.

Bruce Jacob, U. Maryland
Kathy Smiley, Memory Systems
Ameen Akel, Micron
James Ang, Sandia National Labs
Yitzhak Birk, Technion
Bruce Childers, U. Pittsburgh
Zeshan Chishti, Intel
Chen Ding, U. Rochester
David Donofrio, Berkeley Lab
Wendy Elsasser, ARM
Maya Gokhale, LLNL
Thuc Hoang, NNSA/DOE
Hillery Hunter, IBM
Mike Ignatowski, AMD
Aamer Jaleel, NVIDIA
David Kaeli, Northeastern
Scott Lloyd, LLNL
Gabriel Loh, AMD
Kenneth Ma, Hynix
Richard Murphy, Micron
Mike O’Connor, NVIDIA
Petar Radojkovic, BSC
David Resnick, Sandia National Labs
Arun Rodrigues, Sandia National Labs
John Shalf, Berkeley Lab
Anouk Van Laer, U. College London
Jeffrey Vetter, Georgia Tech & ORNL
Robert Voigt, Northrop Grumman
David Wang, Inphi
Christian Weis, U. Kaiserslautern
Kenneth Wright, Rambus
Sudhakar Yalamanchili, Georgia Tech

Call for Papers: Emerging Technologies for Reconfigurable Systems in the Manycore Era

Submitted by Patti Davide
June 27 to June 29, 2016

Submitted by Patti Davide
Emerging Technologies for Reconfigurable Systems in the Manycore Era
Special session in Int’l Symposium on Reconfigurable Communication-centric SoC’s (ReCoSoC 2016)
Tallinn, Estonia
June 27-29, 2016

Abstract submission deadline: April 1, 2016
Full paper submission deadline: April 6, 2016
Author notification: May 15, 2016
Camera-ready due: June 5, 2016

Current multicore architectures formed by tens of processing cores will be
soon replaced by the next generation of manycore architectures with hundreds
of cores. Although manycore architectures are envisaged as the most effective
for meeting the energy and performance constraints which characterize future
applications, some technical and technology aspects start to exacerbate. Dark
silicon, memory wall, on-chip communication scalability, represent just a
short list. Emerging technologies, novel architectures and design techniques,
which stress the reconfiguration concept, are currently investigated by the
research community as viable opportunities for tackling the
performance-in-the-energy-envelop problem in the manycore era.

The aim of this Special Session is to bring together a group of leading
academic researchers and technology experts to provide a platform for
discussion on novel ideas and studies related to design, modelling and
analysis of reconfigurable manycore architectures based on emerging

Authors are invited to submit contributions as maximum 8 page papers in IEEE
conference format. ReCoSoC 2016 follows a double-blind review process:
author’s should not reveal their identity in the manuscript. Contribution(s)
have to be submitted electronically through the EasyChair portal of the
conference at

Davide Patti, Univ. of Catania, Italy,
Maurizio Palesi, Univ. of Enna – KORE, Italy,

Call for Nominations: Eckert-Mauchly Award

Submitted by Milagros
June 18 to June 22, 2016

Submitted by Milagros

2016 ACM/IEEE-CS Eckert-Mauchly Award

Deadline: 30 March 2016

ACM and the IEEE Computer Society co-sponsor the Eckert-Mauchly Award, which
was initiated in 1979. The award is known as the computer architecture
community’s most prestigious award.

The award recognizes outstanding contributions to computer and digital systems
architecture. It comes with a certificate and a $5,000 honorarium.

The award was named for John Presper Eckert and John William Mauchly, who
collaborated on the design and construction of the Electronic Numerical
Integrator and Computer (ENIAC), the first large-scale electronic computing
machine, which was completed in 1947.

This year’s award will be presented at the 43rd International Symposium on
Computer Architecture (ISCA). ISCA will be held in Seoul, South Korea,
June 18-22, 2016.

– Open to all. Do not need IEEE Membership to nominate.
– This award requires 3 endorsements.
– Self-nominations are not accepted.
Additional details at the award web site. Contact for
any questions.

Committee Selection Chair:
Antonio Gonzalez, Universitat Politecnica de Catalunya

2015 Recipient: Norman P. Jouppi, Google
“For pioneering contributions to the design and analysis
of high-performance processors and memory systems.”

2014 Recipient: Trevor Mudge, University of Michigan
“For pioneering contributions to low power computer architecture
and its interaction with technology.”

Call for Participation: MobiTools Tutorial Co-located with ISCA 2016

Submitted by Yuhao Zhu
June 19, 2016

Submitted by Yuhao Zhu

MobiTools: Tutorial on Infrastructure and Tools for Mobile Computer
Architecture Research with an Emphasis on Real System Measurement

co-located with ISCA 2016
Seoul, Korea
June 19, 2016

The tutorial is a step to overcome the increasing barrier of entry for
conducting mobile computer architecture research. We present a series of tools
and infrastructures that enable computer system and architecture research in
the mobile computing space. The tutorial will span three key components of
mobile computing: software, hardware, and end-users. The tools that we will
cover strongly emphasize real system measurement, including performance,
power/energy, and user QoS experience.

Being co-located with ISCA provides an opportunity to have some great invited
speakers and an exciting panel: a great opportunity to see the masterminds
behind mobile computer architecture research.

MobiTools also invites mobile research tool developers to give a thirty minute
presentation about their tool and how to conduct productive research with it.
An ideal presentation will briefly introduce the tool and its underlying
mechanisms and then walk the audience through a (possibly hands on)
“quickstart” tutorial.

Call for Papers: NOCS 2016

Submitted by John Kim
August 31 to September 2, 2016

Submitted by John Kim

10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016)
Nara, Japan
August 31 – September 2, 2016

Abstract registration deadline: February 12, 2016
Full paper submission deadline: February 19, 2016
Notification of acceptance : April 8, 2016
Final version due: May 18, 2016

The International Symposium on Networks-on-Chip (NOCS) is the premier event
dedicated to interdisciplinary research on on-chip, chip-scale, and multichip
package scale communication technology, architecture, design methods,
applications and systems. NOCS brings together scientists and engineers
working on NoC innovations and applications from inter-related research
communities, including computer architecture, networking, circuits and
systems, packaging, embedded systems, and design automation.

Topics of interest include, but are not limited to:

1. NoC Architecture and Implementation:
– Network architecture (topology, routing, arbitration)
– NoC Quality of Service
– Timing, synchronous/asynchronous communication
– NoC reliability issues
– Network interface issues
– NoC design methodologies and tools
– Signaling & circuit design for NoC links

2. NoC Analysis and Verification:
– Power, energy & thermal issues (at the NoC, un-core and/or system-level)
– Benchmarking & experience with NoC-based hardware
– Modeling, simulation, and synthesis of NoCs
– Verification, debug & test of NoCs
– Metrics and benchmarks for NoCs

3. Novel NoC Technologies:
– New physical interconnect technologies, e.g., carbon nanotubes, wireless
NoCs, through-silicon, etc.
– NoCs for 3D and 2.5D packages
– Package-specific NoC design
– Optical, RF, & emerging technologies for on-chip/in-package interconnects

4. NoC Application:
– Mapping of applications onto NoCs
– NoC case studies, application-specific NoC design
– NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
– NoC designs for heterogeneous systems, fused CPU-GPU architectures, etc
– Scalable modeling of NoCs

5. NoC at the Un-Core and System-level:
– Design of memory subsystem (un-core) including memory controllers,
caches, cache coherence protocols & NoCs
– NoC support for memory and cache access
– OS support for NoCs
– Programming models including shared memory, message passing and
novel programming models
– Issues related to large-scale systems (datacenters, supercomputers)
with NoC-based systems as building blocks

6. On-Chip Communication Optimization:
– Communication efficient algorithms
– Multi/many-core communication workload characterization & evaluation
– Energy efficient NoCs and energy minimization

Electronic paper submission requires a full paper, up to 8 double-column IEEE
format pages, including figures and references. The program committee in a
double-blind review process will evaluate papers based on scientific merit,
innovation, relevance, and presentation.

Submitted papers must describe original work that has not been published
before or is under review by another conference or journal at the same time.
Each submission will be checked for any significant similarity to previously
published works or for simultaneous submission to other archival venues, and
such papers will be rejected. Proposals for special sessions, tutorials, and
demos are invited. Paper submissions and demo proposals by industry
researchers or engineers to share their experiences and perspectives are also

Please see the detailed submission instructions for paper submissions, special
session, tutorial, and demo proposals on the conference web site.

General Co-Chairs:
– Hideharu Amano (Keio University, Japan)
– Partha Pratim Pande (Washington State University, USA)

Technical Program Co-Chairs:
– Hiroki Matsutani (Keio University, Japan)
– Sriram Vangal (Intel, USA)

Publicity Co-Chairs:
– John Kim (Korea Advanced Institute of Science and Technology, Korea)
– Turbo Majumder (Intel, USA)
– Maurizio Palesi (Kore University, Italy)

Publication Chair:
– Umit Ogras (Arizona State University, USA)

Industry Chair:
– Yuichiro Ajima (Fujitsu Limited, Japan)

Special Sessions Co-Chairs:
– Michihiro Koibuchi (National Institute of Informatics, Japan)
– Sudeep Pasricha (Colorado State University, USA)

Tutorial Chair:
– Paul Bogdan (University of Southern California, USA)

Finance Chair:
– Ikki Fujiwara (National Institute of Informatics, Japan)

Registration Chair:
– Takashi Nakada (University of Tokyo, Japan)

Local Arrangements Chair:
– Shinya Takamaeda (Nara Institute of Science and Technology, Japan)

Call for Papers: Workshop on Cognitive Architectures

Submitted by Karthik Swaminathan
April 2, 2016 at 13:00

Submitted by Karthik Swaminathan

The 2nd Workshop on Cognitive Architectures (CogArch 2016)
co-located with ASPLOS 2016
Atlanta, Georgia, USA
April 2, 2016

Submission deadline: Feb 15, 2016
Notification: Feb 29, 2016
Camera ready deadline: Mar 30, 2016

Recent advances in Cognitive Computing Systems (as evidenced by innovations
like Watson from IBM and self-driving cars from Google), coupled with
neurally-inspired hardware designs (such as the IBM True North chip), have
spawned new research and development activity in machine learning,
neuromorphic and other brain-inspired computing models, and architectures for
efficient support of complex tasks in computer vision, speech recognition and
artificial intelligence. The proliferation of mobile computing platforms, IoT
and cloud support features thereof have opened up exciting new opportunities
for real-time, mobile (distributed or swarm-driven) cognition. This half-day
workshop solicits formative ideas and new product offerings in this general

Topics of interest include (but are not limited to):
– Algorithms in support of cognitive reasoning: recognition, intelligent
search, diagnosis, inference and informed decision-making.
– Swarm intelligence and distributed architectural support; brain-inspired and
neural computing architectures.
– Accelerators and micro-architectural support for cognitive computing.
– Cloud-backed autonomics and mobile cognition: architectural and OS support
– Resilient design of distributed (swarm) mobile cognitive architectures.
– Energy efficiency, battery life extension and endurance in mobile, cognitive
– Case studies and real-life demonstrations/prototypes in specific application
domains: e.g. Smart homes, connected cars and UAV-driven commercial services,
as well as applications of interest to defense and homeland security.

The workshop shall consist of short presentations by authors of selected
submissions. In addition, it will include invited keynotes by eminent
researchers from industry and academia as well as interactive panel
discussions to kindle further interest in these research topics. Submitted
papers will be reviewed by a workshop program committee, in addition to
the organizers. Submissions are limited to 6 pages, including references,
with same formatting guidelines as main conference.

Karthik Swaminathan, Augusto Vega, Alper Buyuktosunoglu, Pradip Bose –
IBM T.J Watson Research Center
Vijaykrishnan Narayanan – Pennsylvania State University

Call For Papers: Workshop on Multicore and Rack-scale Systems

Submitted by Boris Grot
February 5, 2016

Submitted by Boris Grot

Workshop on Multicore and Rack-scale Systems (MARS)
co-located with EuroSys 2016
London, UK
April 18, 2016

Submission deadline: February 5, 2016
Acceptance Notification: March 9, 2016
Workshop date: April 18, 2016

Present and future multi-core architectures pose a variety of challenges for
system developers: non-cache-coherent memory, heterogeneous processing cores
and the exploitation of novel architectural features, such as systems-on-chip
(SoCs), distributed switching fabrics, silicon photonics, and programmable
hardware. In the near future, we expect to see “rack-scale computers” with
1,000s of cores and terabytes of memory, connected with bandwidth and latency
comparable to today’s smaller-scale NUMA servers.

MaRS 2016 is a forum for researchers in the hardware, networking, storage,
operating systems, language runtime and virtual machine communities to present
their experiences with and discuss innovative designs and implementations for
these new architectures.

Topics of interest include, but are not limited to:
– novel multi-core and rack-scale operating system designs,
– System-on-chip (SoC) and Network-on-chip (NoC) designs,
– runtime systems and programming environments for future hardware,
– low-latency and optical networking,
– OS or runtime support for heterogeneous processing cores,
– non-cache-coherent shared memory,
– scheduling on many-core and rack-scale architectures,
– programmable hardware,
– energy efficiency, fault tolerance and resource management on
future multi-core and rack-scale architectures,
– rack-scale storage,
– performance evaluation of emerging hardware,
– architectural support for systems-level software,
– case studies of system-level software design for current or future
multi-core and rack-scale hardware, and
– applications for and experiences with multi-core and rack-scale

Authors are invited to submit original and unpublished work that exposes a
new problem, advocates a specific solution, or reports on actual experience.
Papers should be submitted using the standard two-column ACM SIG proceedings
or SIG alternate template, and are limited to 5 pages (including everything
except references). Additional pages can be used for references if required.
Papers that violate the submission guidelines may be rejected without
consideration of their merit.

Final papers will be made available to participants electronically at the
meeting, but to facilitate resubmission to more formal venues, no archival
proceedings will be published, and papers will not be sent to the ACM Digital
Library. Authors will be given the option of having their final paper
accessible from the workshop website. Authors of accepted papers will be
invited to give a talk at the workshop.

If you are interested in giving a talk at MaRS 2016, please submit a one-page
abstract instead of a full paper. Authors of accepted papers/talks will also
be invited to present a poster and/or demo in the EuroSys ’16 joint poster
session. Student speakers will be eligible to apply for EuroSys travel grants
to attend.

Boris Grot (University of Edinburgh)
Simon Peter (UT Austin)
Chris Rossbach (VMware and UT Austin)

Program Committee:
Mahesh Balakrishnan (Yale)
Antonio Barbalace (Virginia Tech)
Taesoo Kim (Georgia Tech)
Mark Oskin (University of Washington)
Mark Silberstein (Technion)
Cheng-Chun Tu (VMware)
John Wilkes (Google)
Bernard Wong (University of Waterloo)

Call for Papers: Workshop on Heterogeneous and Unconventional Cluster Architectures and Applications

Submitted by Federico Silla
August 16, 2016

Submitted by Federico Silla

5th International Workshop on Heterogeneous and Unconventional
Cluster Architectures and Applications (HUCAA 2016)

in conjunction with ICPP 2016
Philadelphia, PA, USA
August 16, 2016

Paper submission: March 21, 2016
Notification of acceptance: May 13, 2016
Camera-ready paper: June 3, 2016
Workshop: August 16, 2016

The workshop on Heterogeneous and Unconventional Cluster Architectures and
Applications gears to gather recent work on heterogeneous and unconventional
cluster architectures and applications, which might have an impact on future
mainstream cluster architectures. This includes any cluster architecture that
is not based on the usual commodity components and therefore makes use of
some special hard- or software elements, or that is used for special and
unconventional applications. In particular we call for GPUs and other
accelerators (Intel MIC/Xeon Phi, FPGA) used at cluster level. Even though
accelerators are already used pervasively, we still see many unconventional
and even disruptive uses of them.

Other examples of unconventional cluster architectures and applications
include virtualization, in-memory storage, hard- and software interactions,
run-times, databases, and device-to-device communication. We are in
particular encouraging work on disruptive approaches, which may show inferior
performance today but can already point out their performance potential. The
broad scope of the workshop facilitates submissions on unconventional uses of
hardware or software, gearing to gather ideas that are coming to life now and
not limiting them except for their context: clusters. Also, these proposals
may rather be reflective of a broader industry trend.

Topics of interest include any heterogeneous or unconventional cluster
architecture or application. Examples include, but are not limited to:
– Clustered GPUs, Xeon Phis or other accelerators
– Runtimes, resource management and scheduling for heterogeneous cluster
– Communication methods for distributed or clustered accelerators
– Energy-aware data movement techniques
– Energy efficiency at the cluster or node level
– New industry and technology trends and their potential impact
– High-performance, data-intensive, and power-aware computing
– Application-specific cluster and datacenter architectures
– Emerging programming paradigms for parallel heterogeneous computing
– Software cluster-level virtualization for consolidation purposes
– Hardware techniques for resource aggregation
– New uses of GPUs, FPGAs, and other specialized hardware

Submissions may not exceed 8 pages in PDF format including figures and
references, and must be formatted in the 2-column IEEE format. Submitted
papers must be original work that has not appeared in and is not under
consideration for another conference or journal. Work in progress is welcome,
but first results should be made available as a proof of concept. Submissions
only consisting of a proposal will be rejected. Please visit the workshop
website for additional details.

Workshop Co-Chairs:
– Federico Silla, Technical University of Valencia, Spain
– Holger Fröning, U. Heidelberg, Germany

Program Committee:
– Tarek Abdelrahman, U. Toronto, Canada
– José Luis Abellán, Catholic University of Murcia, Spain
– Olivier Aumage, INRIA, France
– José María Cecilia, Catholic University of Murcia, Spain
– Pierfrancesco Foglia, University of Pisa, Italy
– Basilio Fraguela, U. Coruna, Spain
– Efstratios Gallopoulos, University of Patras, Greece
– Marc Gonzalez, Universitat Politecnica de Catalunya, Spain
– Sascha Hunold, Technical University of Vienna, Austria
– Christos Kartsaklis, Oak Ridge National Lab, US
– Christoph Kessler, Linköping University, Sweden
– Tomàs Margalef, U. Autonoma Barcelona, Spain
– Gaspar Mora, Intel, US
– Thu D. Nguyen, U. Rutgers, US
– Dimitrios S. Nikolopoulos, Queen’s University, Belfast, UK
– Lena Oden, Argonne National Labs, US
– Alberto Ros, University of Murcia, Spain
– Dirk Pleiter, Research Center Jülich, Germany
– Alistar Rendell, Australian National University, Australia
– Etienne Riviere, University of Neuchatel, Switzerland
– Won Ro, Yonsei University, South Korea
– Antonio Robles, Technical University of Valencia, Spain
– Douglas Thain, U. Notre Dame, US
– Matthew Jacob Thazhuthaveetil, Indian Institute of Science, India
– Blesson Varghese, U. St Andrews, UK
– Shuangyang Yang, Louisiana State University, US

Steering Committee:
– José Duato, Technical University of Valencia, Spain
– Sudhakar Yalamanchili, Georgia Tech, US
– Ulrich Brüning, U. Heidelberg, Germany

Call for Papers: IEEE Micro Special Issue on Security

Submitted by jayvant anantpur

Submitted by jayvant anantpur

IEEE Micro Special Issue on Security

Guest Co-Editors:
Mohit Tiwari, The University of Texas at Austin
Todd Austin: University of Michigan, Ann Arbor

Submissions due: Feb 26, 2016
Publication date: Sept/Oct 2016

Secure, networked systems are the foundation on which the future
healthcare, finances, automotives, and other intelligent services will rest.
Currently deployed systems, from implanted medical devices to voting
machines to mobile phones and data centers, have all been shown to be
vulnerable, and new architectures are required to construct a trustworthy
computing infrastructure.

This Special Issue on Security seeks papers on a range of topics, including but
not limited to:

– Isolation and Access control, Virtualization
– Capabilities
– Information flow control
– Cryptographic primitives
– Side channel and physical access (power, EM, etc.) attacks and defenses
– Attestation and trusted/tamper-proof execution, enclaves, etc.
– Malware detection
– Network processors and deep packet analysis
– Accelerators for security analytics
– Introspection, debugging, root cause analysis
– Secure storage, e.g. using emerging non-volatile memories
– Programming languages and formal design tools for secure architectures
– Metrics and evaluation methodologies for secure architectures
– Secure architectures for domains such as voting machines, medical devices,
automotives, high assurance embedded systems, data centers, and IoT

Initial submissions due: Feb 26, 2016
Initial notifications: April 29, 2016
Revised papers due: May 20, 2016
Final notifications: June 10, 2016
Final versions due: June 24, 2016
Publication date: Sept/Oct 2016

Log onto IEEE CS Manuscript Central (
and submit your manuscript. Please direct questions to the IEEE Micro magazine
assistant (micro­ regarding the submission site. For the
manuscript submission, acceptable file formats include Microsoft Word and PDF.
Manuscripts should not exceed 5,000 words including references, with each
average­-size figure counting as 250 words toward this limit. Please include
all figures and tables, as well as a cover page with author contact information
(name, postal address, phone, fax, and e­mail address) and a 200­-word
abstract. Submitted manuscripts must not have been previously published or
currently submitted for publication elsewhere, and all manuscripts must be
cleared for publication. All previously published papers must have at least 30%
new content compared to any conference (or other) publication. Accepted
articles will be edited for structure, style, clarity, and readability. For
more information, please visit the IEEE Micro Author Center.

Questions: Please contact Guest co-Editors Mohit Tiwari
( and Todd Austin (, or
Editor-in-Chief Lieven Eeckhout (