Call for Papers: Workshop on Accelerators and Hybrid Exascale Systems

The Seventh International Workshop on Accelerators and Hybrid Exascale Systems (AsHES)
http://www.mcs.anl.gov/events/workshops/ashes/2017
in conjunction with IPDPS’17
Orlando, Florida, USA
May 29, 2017

IMPORTANT DATES:
Paper Submission: Jan. 13, 2017 (AoE)
Paper Notification: Feb. 15, 2017
Camera-Ready: Feb. 25, 2017

Current and emerging systems are deployed with heterogeneous architectures and accelerators of more than one type (e.g., GPGPU, Intel® Xeon Phi™, FPGA) along with hybrid processors of both lightweight and heavyweight cores (e.g., APU, big.LITTLE). Such architectures also comprise hybrid memory systems equipped with stacked/hierarchical memory and non-volatile memory in addition to regular DRAM. Programming such a system can be a real challenge along with locality,
scheduling, load balancing, concurrency and so on.

This workshop focuses on understanding the implications of accelerators and heterogeneous designs on the hardware systems, porting applications, performing compiler optimizations, and developing programming environments for current and emerging systems. It seeks to ground accelerator research through studies of application kernels or whole applications on such systems, as well as tools and libraries that improve the performance and productivity of applications on these systems. The goal of the workshop is to bring together researchers and practitioners who are involved in application studies for accelerators and other heterogeneous systems, to learn the opportunities and challenges in future design trends for HPC applications and systems.

Topics of interest for workshop submissions include (but are not limited to):
– Strategies for programming heterogeneous systems using high-level models such as OpenMP and OpenACC, and low-level models such as OpenCL, CUDA;
– Methods and tools to tackle challenges in scientific computing at extreme scale;
– Strategies for application behavior characterization and performance optimization for accelerators;
– Techniques for optimizing kernels for execution on GPGPU, Intel Xeon Phi and future heterogeneous platforms;
– Models of application performance on heterogeneous and accelerated HPC systems;
– Compiler Optimizations and tuning heterogeneous systems including parallelization, loop transformation, locality optimizations, Vectorization;
– Implications of workload characterization in heterogeneous and accelerated architecture design;
– Benchmarking and performance evaluation for accelerators;
– Tools and techniques to address both performance and correctness to assist application development for accelerators and heterogeneous processors;
– System software techniques to abstract application domain-specific functionalities for accelerators;

Keynote Speaker:
Tim Mattson (Intel) will give a keynote speech at AsHES 2017.

SUBMISSION GUIDELINES:
Papers should present original research and should provide sufficient background material to make them accessible to the broader community. Submitted manuscripts may not exceed 10 single-spaced double-column pages using 10-point size font on 8.5×11 inch pages (IEEE conference style), including figures, tables, and references. See the style templates for latex or word for details.

Submissions will be judged based on relevance, significance, originality, correctness and clarity.
Submission site: https://easychair.org/conferences/?conf=ashes17

The proceedings of this workshop will be published electronically together with IPDPS proceedings via the IEEE Xplore Digital Library.

ORGANIZERS:
General Chair:
Sunita Chandrasekaran, University of Delaware, USA

Program Co-Chairs:
Antonio J. Peña, Barcelona Supercomputing Center, Spain
Sangmin Seo, Argonne National Laboratory, USA

Program Committee:
Ashwin Aji, AMD, USA
James Beyer, NVIDIA Corporation, USA
Huimin Cui, Institute of Computing Technology, CAS
Anthony Danalis, University of Tennessee, USA
Khaled Hamidouche, The Ohio State University, USA
Jeff Hammond, Intel Labs, USA
Siva Kumar Sastry Hari, NVIDIA Corporation, USA
Hennry Jin, NASA, USA
Guido Juckeland, HZDR, Germany
Sriram Krishnamoorthy, Pacific Northwest National Laboratory, USA
Seyong Lee, Oak Ridge National Laboratories, USA
Dong Li, University of Calfornia, Merced, USA
John Lidel, Texas Tech University, USA
Piotr Luszczek, University of Tennessee, USA
Naoya Maruyama, RIKEN AICS, Japan
Stephen Olivier, Sandia Nationl Lab, USA
Kelly Shaw, University of Richmond, USA
Xipeng Shen, North Carolina State University, USA
Min Si, Argonne National Laboratory, USA
Bronis de Supinski, Lawrence Livermore National Laboratory, USA
Hao Wang, Virginia Tech, USA
Yongpeng Zhang, Stone Ridge Technology, USA

Steering Committee:
Pavan Balaji, Argonne National Laboratory, USA
Yunquan Zhang, Chinese Academy of Sciences, China
Satoshi Matsuoka, Tokyo Institute of Technology, Japan
Jiayuan Meng, Argonne National Laboratory, USA
Xiaosong Ma, Qatar Computing Research Institute, Qatar
Barbara Chapman, University of Houston, USA
Guang R. Gao, University of Delaware, USA
Xinmin Tian, Intel, USA
Michael Wong, IBM, Canada
James Dinan, Intel Corporation

QUESTIONS?
Please send any queries about the AsHES workshop to ashes@mcs.anl.gov

Call for Submissions: Intel Hardware Accelerator Research Program v2

Submission Deadline: Oct 21, 2016

Intel Corporation is pleased to announce the second round of the Hardware Accelerator Research Program, which will provide faculty with access to computer systems containing Intel microprocessors and an Altera Arria-10 FPGA in a multi-chip package (MCP) that incorporates Intel’s Accelerator Abstraction Layer Software in order to spur research in programming tools, operating systems, and innovative applications for accelerator-based computing systems.

In recent years, accelerators and coprocessors have attracted a great deal of interest, but the effort required to program heterogeneous systems has limited their impact. Current programming tools for these technologies require a great deal of domain-specific knowledge to reformulate algorithms for FPGA, partition a design between FPGA and CPU, and orchestrate data transfers between FPGA and CPU. In addition, portability still remains a challenge between different CPU+FPGA systems.

In order to improve the usability of these systems, Intel Corporation is interested in research into tools, applications, and methodologies that:
– Reduce the amount of effort required to map an application onto a coprocessor or accelerator
– Operating systems and schedulers that can automatically assign tasks to the most efficient hardware in a heterogeneous system
– Techniques to make applications portable across different hardware technologies
– Innovative applications that demonstrate the potential of heterogeneous systems.

To support and encourage this research, the Hardware Accelerator Research Program is making systems available to researchers that pair a 12-core Intel microprocessor with an Altera Arria10 FPGA.
Intel plans to build approximately 30 next-generation Hardware Accelerator Research Program systems (Broadwell + Arria10). These systems will be provided through two allocations:
1. To enable distributed-systems and data-center research, systems will be placed in centralized cluster installations in the U.S. and Europe (20 nodes total, 10 nodes per installation). The clusters will be made available via remote access to eligible program participants.
2. Several systems will be provided to researchers who need physical access to the platform based on their research agenda.

Researchers awarded access to Hardware Accelerator Research Program systems may also qualify for a license to use the Altera Quartus Design Software and other software tools free of charge.

Additionally, researchers awarded access to Hardware Accelerator Research Program systems will be invited to a series of workshops to be held at Intel campuses. The first workshop, to be held in late 2016 and will include tutorials on Intel’s Accelerator Abstraction Layer Software and provide basic training on how to develop hardware/software for the system. It will also give researchers an opportunity to discuss ideas for research using the Hardware Accelerator Research Program systems. Later workshops will provide a forum for researchers to present the results of their work and discuss opportunities for technology transfer with Intel researchers and product designers.

Topics of interest to this CFP include, but are not limited to:
1) Applications and algorithms, e.g.
– Studies of algorithm/application/library design, remapping, and tuning to exploit different aspects of the Hardware Accelerator Research Program MCP system, with a special focus on leveraging close accelerator coupling, cache coherency, and partial reconfiguration and the Accelerator Abstraction Layer
– Techniques to evaluate the applicability and efficiency of algorithms on different components of a reconfigurable heterogeneous architecture and to select the most effective hardware for different phases of an application
– Approaches to simplify and partially automate design, development, deployment, and/or performance characterization of applications to closely-coupled heterogeneous systems

2) Operating system integration and data center scaling, e.g.
– Operating system integration and scheduling techniques for dynamically reconfigurable accelerator-based systems, including shared access, virtualization, and migration of workloads
– Scaling approaches for cluster-level deployments of heterogeneous systems, including orchestration frameworks leveraging the platform’s re-configurability and the Accelerator Abstraction Layer’s service-oriented architecture

3) Domain-specific languages and high-level design, e.g.
– Languages and libraries for coprocessor and accelerator design and development, including domain-specific languages and other high-level design methods
– Analysis of domain- or language-specific characteristics that map to the Hardware Accelerator Research Program platform’s characteristics (i.e. partial re-configurability, close accelerator coupling, cache-coherent memory model).
– Automated HW/SW partitioning approaches that exploit the benefits of low-latency cache-coherent communication between CPU and accelerators

We welcome research proposals from academic institutions new to the program. At the same time, we specifically encourage participants in the first round of Hardware Accelerator Research Program to submit research proposals that build upon and extend the research performed within that program.

We also welcome and encourage applicants to include ideas on how to integrate reconfigurable heterogeneous platforms into their coursework/curriculum alongside their scientific research proposals.

ELIGIBILITY:
To be eligible for this program, proposers must be associated with a non-profit college, university, or research institution. U.S. export regulations prohibit the export of goods and services to Cuba, Iran, North Korea, Sudan and Syria. Therefore, residents or nationals of these countries are not eligible to participate. Proposer and their institution must not be listed on a denial order published by the U.S. Government or any other applicable Government. We welcome proposals from individual researchers, groups, and centers. As part of our evaluation of submitted proposals, we will decide whether successful proposals will be awarded access to the cluster installations closest to their location, or whether successful proposals will receive a single Hardware Accelerator Research Program system.

Proposals will be evaluated on technical merit, potential impact of the proposed research, the proposer’s ability to carry out the proposed research, and potential for collaboration with Intel researchers. Submitters of successful proposals will be expected to sign an agreement not to resell the donated equipment for a period of three years, to make results of their work available to Intel, and to participate on the program’s web forum by giving feedback about their experiences with the Hardware Accelerator Research Program platforms.

Each Recipient must acknowledge that donated equipment is subject to export controls under U.S. and other applicable Government laws and regulations. Recipient will comply with these laws and regulations governing export, re-export, import, transfer, distribution, use, and servicing of donated equipment, and agree to obtain all required Government authorizations. Recipient will not sell or transfer donated equipment to any entity listed on a denial order published by Government, or a country subject to sanctions, without first obtaining a license or authorization. Recipient will not use, sell, or transfer donated equipment for purposes prohibited by Government, including, without limitation, the development, design, manufacture, or production of nuclear, missile, chemical or biological weapons, unless authorized by a specific license. For more details on your export obligations, please visit http://www.intel.com/content/www/us/en/legal/export-compliance.html.

SUBMISSION INSTRUCTIONS:
Interested parties should submit a proposal of at most two 8.5″x11″ pages, in at least 10pt font, to hw_accelerator_research_program@intel.com by midnight Pacific Standard Time (UTC-8) on October 21, 2016. Proposals should be in PDF format, and should include the name and institution of the individual(s) requesting the platform, a description of the research that will be performed using the platform, and a brief summary of the requestor’s relevant previous work, if any.

Call for Participation: Tutorial on Quantum Computing

Tutorial: From Quantum Bits to Quantum Computing
in conjunction with HPCA
Austin, USA
February 5, 2017

Quantum computers hold the promise for solving efficiently important problems in computational sciences that are intractable nowadays by exploiting quantum phenomena such are superposition and entanglement. One of the most famous examples is the factorization of large numbers using Shor’s algorithm. For instance, a 2000-bit number could be decomposed in a bit more than one day using a quantum computer whereas a data center of approx. 400.000 Km2 built with the fastest today’s supercomputer would require around 100 years.

This tutorial will introduce the basic notions of quantum computing and will address the main challenges when building a large-scale quantum computer. The tutorial will provide hands-on exercises based on the QX simulator platform and will allow participants to understand what quantum circuits and quantum gates are.

Topics:
-Overview of quantum computing, as compared to classical computing
-Universal quantum gates and quantum circuits
-Quantum error correction
-Quantum computer architecture
-Exercises writing small quantum circuits using the QX simulation platform

ORGANIZERS:
Koen Bertels, Delft University of Technology, NL
Carmen G. Almudever, Delft University of Technology, NL

Call for Presentations: Systems Support for Big Data Applications

Systems Support for Big Data Applications
https://www.hipeac.net/events/activities/7412/systems-support-for-big-data-applications
in conjuction with HiPEAC Autumn Computing Systems Week
Dublin, Ireland
November 7, 2016

Submission Deadline: October 21, 2016.

We are now living in a world of Big Data. The ability to process and analyse large data sets is revolutionising the way we live, work and socialise. Building software and hardware systems that can process big data with high throughput is thus a critical task for the research community and industry. Hardware and software solutions to address the problem of how to program, optimise and manage Big Data applications form the core topic of this session.

Topics of interest for this session include, but are not limited to, recent results and demonstrations, involving:
– Novel hardware systems for data intensive applications
– Programming languages and models for Big Data applications
– Compilers and tools for Big Data optimisation
– Runtime and operating systems for Big Data applications
– Middleware and software architecture for Big Data
– Big Data applications

If you are interested in giving a presentation, send an email to Vicent Sanz Marco (v.sanzmarco@lancaster.ac.uk) and Pavlos Petoumenos (ppetoume@inf.ed.ac.uk) with a 200-word abstract by Friday, 21st of October, 2016.

Talks from industrial partners are particularly welcome.

Call for Papers: ARCS 2017

30th International Conference on Architecture of Computing Systems (ARCS 2017)
http://arcs2017.itec.kit.edu/
Vienna, Austria
April 3-6, 2017

IMPORTANT DATES:
Paper submission deadline: October 28, 2016
Workshop and tutorial proposals: November 30, 2016
Notification of acceptance: December 21, 2016
Camera-ready papers: January 11, 2017

The ARCS conferences series has over 30 years of tradition reporting leading edge research in computer architecture and operating systems. The focus of the 2017 conference will be on Heterogeneous Node Architectures with Deep Memory Systems. ARCS 2017 will be organized by the Complang Group at the Vienna University of Technology and the CAPP group at the Karlsruhe Institute of Technology (KIT).

Authors are invited to submit original, unpublished research papers on one or more of the following topics:
– Multi-/many-core architectures, memory systems, and interconnect networks
– Programming models, runtime systems, and middleware support for many-core and/or heterogeneous computing platforms
– Tool support for performance optimization, debugging, and verification
– Generic and application-specific architectures such as reconfigurable systems in hardware and software
– Robust and fault-tolerant systems structures
– Architectures and design methods/tools for real-time embedded systems
– Cyber-physical systems and distributed computing architectures
– Organic and autonomic computing including both theoretical and practical results on self-organization, self-configuration, self-optimization, self-healing, and self-protection techniques
– Operating Systems, including but not limited to scheduling, memory management, power management, and real-time OS (RTOS) concepts
– Energy and power-aware computing, including green computing topics
– System aspects of ubiquitous and pervasive computing such as sensor nodes, novel input/output devices, novel computing platforms, architecture modeling, and middleware
– Architectures for robotics and automation systems
– Applications of embedded and cyber-physical systems
– High-performance and large scale parallel computing
– Approximate computing
– Post-Moore Architectures, including but not limited to quantum and neuromorphic computing

SUBMISSION GUIDELINES:
Submissions should be done through the link that is provided on the conference website. Papers must be submitted in PDF format. They should be formatted according to Springer LNCS style and must not exceed 12 pages, including references and figures.

The proceedings of ARCS 2017 will be published in the Springer Lecture Notes on Computer Science (LNCS) series. After the conference, it is planned that authors of selected papers will be invited to submit an extended version of their contribution for publication in a special issue of the Journal of Systems Architecture. Further, a best paper and best presentation award will be presented at the conference.

WORKSHOP AND TUTORIAL PROPOSALS:
Proposals for workshops and tutorials within the technical scope of the conference are solicited. Submissions should be done through email directly to the corresponding chair: Carsten Trinitis (Carsten.Trinitis@tum.de)

ORGANIZING COMMITTEE:
General Co-Chairs:
Jens Knoop, Vienna University of Technology, Austria
Wolfgang Karl, Karlsruhe Institute of Technology, Germany

Program Co-Chairs:
Martin Schulz, Lawrence Livermore National Laboratory, USA
Koji Inoue, Kyushu University, Japan

Workshop and Tutorial Co-Chairs:
Carsten Trinitis, Technische Universität München, Germany

Publicity Chair:
Miquel Pericàs, Chalmers University of Technology, Sweden

Publication Chair:
Thilo Piontek, Magdeburg University, Germany

Call for Papers: MULTIPROG 2017

The Tenth International Workshop on Programmability and Architectures for Heterogeneous Multicores (MULTIPROG-2016)
http://research.ac.upc.edu/multiprog/
in conjunction with HiPEAC
Stockholm, Sweden
January 24, 2017

IMPORTANT DATES:
Paper submission: October 21, 2016
Author notification: November 27, 2016

The ninth edition of the MULTIPROG workshop aims to bring together researchers interested in programming models, runtimes, and computer architecture. The workshop’s emphasis is on heterogeneous architectures and covers issues such as:
– How can future parallel programming models improve software productivity?
– How should compilers, runtimes and architectures support programming models and emerging applications?
– How to design efficient data structures and innovative algorithms?

MULTIPROG is intended for quick publication of early results, work-in-progress, etc., and is not intended to prevent later publication of extended papers. Informal proceedings with accepted papers will be made available at the workshop and online at the workshop’s web page.

Papers are sought on topics including, but not limited to:
1) Multi-core architectures
– Architectural support for compilers/programming models
– Processor (core) architecture and accelerators, in particular GPUs
– Memory system architecture
– Performance, power, temperature, and reliability issues
2) Heterogeneous computing
– Algorithms and data structures for heterogeneous systems
– Applications for heterogeneous computing and real-time graphics
3) Programming models for multi-core architectures
– Language extensions
– Run-time systems
– Compiler optimizations and techniques
4) Benchmarking of multi-/many-core architectures
– Tools for discovering and understanding parallelism
– Tools for understanding performance and debugging
– Case studies and performance evaluation

SUBMISSION GUIDELINES:
Submissions should not exceed 12 pages and should be formatted according to the LNCS format for CS Proceedings. This limit includes text, figures, tables and references. Please visit the workshop web site for detailed submission instructions.

ORGANIZERS:
Miquel Pericàs, Chalmers University of Technology
Vassilis Papaefstathiou, FORTH
Oscar Palomar, University of Manchester
Ferad Zyulkyarov, Barcelona Supercomputing Center

Program committee:
Abdelhalim Amer, Argonne National Lab
Ali Jannesari, UC Berkeley
Avi Mendelson, Technion
Chris Adeyeni-Jones, ARM
Christos Kotselidis, University of Manchester
Dong Ping Zhang, AMD
Håkan Grahn, Blekinge TH
Hans Vandierendonck, Queen’s University Belfast
Kenjiro Taura, University of Tokyo
Magnus Sjalander, NTNU
Oscar Plata, University of Malaga
Pedro Trancoso, University of Cyprus
Polyvios Pratikakis, FORTH-ICS
Roberto Gioiosa, PNNL
Sasa Tomic, IBM Research
Timothy G. Mattson, Intel
Trevor E. Carlson, Uppsala University
Yungang Bao, ICT-CAS

Call for Papers: ISCA 2017

The 44th ACM/IEEE International Symposium on Computer Architecture (ISCA)
http://isca17.ece.utoronto.ca/doku.php
Toronto, Canada
June 25-28, 2017

IMPORTANT DATES
– Abstract Deadline: November 11, 2016, 11:59:59PM EST (Mandatory)
– Final Submission Deadline: November 18, 2016, 11:59:59PM EST no extensions
– Rebuttal Period: Early/mid February 2017
– Author Notification: March 8, 2017
– Final Manuscript Submission: May 1, 2017
– Early Registration Deadline: May 1, 2017

The International Symposium on Computer Architecture is the premier forum for new ideas and experimental results in computer architecture. The conference specifically seeks particularly forward-looking and novel submissions. Papers are solicited on a broad range of topics, including (but not limited to):
– Processor, memory, and storage systems architecture
– Parallel and multicore systems
– Data-center scale computing
– Architectures for handheld and mobile devices
– Application-specific, reconfigurable, or embedded architectures
– Accelerator-based architectures
– Architectures for security and virtualization
– Power and energy efficient architectures
– Interconnection networks
– Instruction, thread, and data-level parallelism
– Dependable architectures
– Architectural support for programming productivity
– Network processor and router architectures
– Architectures for emerging technologies and applications
– Effect of circuits and technology on architecture
– Architecture modeling and simulation methodology
– Performance evaluation and measurement of real systems

ORGANIZERS:
– General Chair: Andreas Moshovos, University of Toronto
– Program Chair: David Brooks, Harvard University
– Finance Chair: Mike Ferdman, University of New York, Stony Brook
– Tutorials Chair: Paul Gratz, Texas A&M
– Workshops Chair: TBD
– Publicity Chair: Christina Delimitrou, Cornell University
– Web and Social Media Chair: Gennady Pekhimenko, MSR and University of Toronto
– Publications Chair: Mahdi Bojnordi, University of Utah
– Student Travel Awards Chair: Natalie Enright Jerger, University of Toronto
– Registrations Chair: Adrian Sampson, Cornell University
– Industry Laison Chair: TBD

Program Committee:
TBA

Call for Nominations: Athena Lecturer Award

Athena Lecturer Award
http://awards.acm.org/athena/nominations.cfm

Nomination Deadline: November 30, 2016

The Athena Lecturer Award celebrates women researchers who have made fundamental contributions to Computer Science. To date, 11 awards have been given: http://awards.acm.org/athena/all.cfm

In the past, this award was an ACM-W award and SIG officers were responsible for nominating the candidates each year. This year, however, the Athena Lecture Award moves from being an ACM-W award to being an ACM award, operating under the guidelines and structure of other ACM Awards. The nomination deadline is now November 30 and nominations no longer come through the SIGS but come through the standard online nominating form for all ACM awards:
http://awards.acm.org/athena/nominations.cfm and https://campus.acm.org/public/awards/nomination.cfm

Call for Papers: Special Issue of IEEE Micro — Top Picks 2017

Special Issue of IEEE Micro: Micro’s Top Picks from the 2016 Computer Architecture Conferences
https://sites.google.com/site/ieeemicro/call-for-papers/top-picks-2017—call-for-papers
May/June 2017

IMPORTANT DATES:
Submission Deadline: September 19, 2016 (11:59:59 pm EDT)
Author Notification: December 20, 2016
Final Papers Due: January 23, 2017
Publication Date: May/June 2017

IEEE Micro will publish its yearly “Micro’s Top Picks from the Computer Architecture Conferences” as its May / June 2017 issue. This issue collects some of this year’s most significant research papers in computer architecture based on novelty and potential for long-term impact. Any computer architecture paper (not a combination of papers) published in the top conferences of 2016 (including MICRO-49) is eligible. The Top Picks committee will recognize those significant and insightful papers that have the potential to influence the work of computer architects for years to come.

SUBMISSION GUIDELINES:
To simplify reviewing, there is a mandatory format for submissions. The submission website allows uploading two documents per submission. Please upload the following two documents separately as a single submission:

1. A three-page, two-column document using 10-point type. The first two pages should summarize the paper. The third page should argue for the potential of the work to have long-term impact, clearly articulating why and how it will influence other researchers and/or industry. In the third page, please also include what the citation of your paper would be if it won the test of time award in 10 years.

2. The final version of the original conference paper.

Submissions that do not follow this format will not be reviewed. The first document should contain the names of the authors with a footnote that contains the title of the original conference paper, with the full name of the conference, page numbers, and date of publication.

ACCEPTED PAPER GUIDELINES:
Authors of accepted papers will receive further instructions on how to prepare the final papers to conform to IEEE Micro’s guidelines. Final papers should not exceed 5,000 words including references, with each average-size figure counting as 250 words toward this limit. Papers must have at least 30% new content compared to the original conference publication. Final papers will be edited for structure, style, clarity, and readability.

ORGANIZERS:
Special Issue Guest Editors (and Selection Committee Co-Chairs):
Aamer Jaleel, NVIDIA
Moinuddin Qureshi, Georgia Tech

Selection Committee:
TBD

Call for Participation: IISWC 2016

The 2016 IEEE International Symposium On Workload Characterization (IISWC)
http://www.iiswc.org
Providence, Rhode Island, USA
Sep 25-27, 2016

IMPORTANT DATES:
Early Registration Deadline: Sep 12, 2016
Hotel Reservation Deadline: Sep 12, 2016

IISWC provides a high-quality international forum to bring together researchers and practitioners from academia and industry to discuss cutting-edge research on understanding and characterization of workloads that run on all types of computing systems. Whether they are smart phones and deeply embedded systems at the low end or massively parallel systems at the high end, the design of future computing machines can be significantly improved if we understand the
characteristics of the workloads that are expected to run on them.

IISWC registration site: https://www.regonline.com/Register/Checkin.aspx?EventID=1855835

Keynote speakers:
Ravi Iyer, Intel
Alanson Sample, Disney Research

The conference program is available online at http://www.iiswc.org/iiswc2016/program2016.html

IISWC is sponsored by IEEE Computer Society and the Technical Committee on Computer Architecture.