My research focuses on Computer Architectures and Electronic Design Automation, with emphasis on power-aware design for embedded systems, design space exploration of energy-efficient computer architectures and application autotuning for manycore architectures and High-Performance Computing. In 2017, I have been elevated to the grade of IEEE Fellow “for contributions to energy-efficient computer architectures”. Recently I was European Project Coordinator of the H2020-FET-HPC project ANTAREX-671623 (2015-2018) on "Autotuning and adaptivity approach for energy efficient exascale HPC systems”. I was Project Coordinator of two other European projects: FP7-2PARMA-248716 (2010-2013) and FP7-MULTICUBE-216693 (2008-2010). I am an active member of the scientific community and I regularly serve in several international program committees. I annually teach basic and advanced courses on computer architectures and operating systems.

Darya Mikhailenko is pursuing a PhD in Electrical and Computer Engineering at the University of Rochester under the supervision of Prof. Engin Ipek. Her interests cover areas of energy-efficient computer architectures, machine learning for computer vision applications, memory management, accelerators, and architecture modeling for emerging technologies. Darya worked as a research assistant at Nanoelectronics Research Laboratory (Purdue University, U.S.A.) and Bioinspired Microelectronics Systems Laboratory (Nazarbayev University, Kazakhstan) on the implementation of brain-computer architecture to actualize deep neural networks. Her recent work was dedicated to techniques to minimize data movement energy by exploiting asymmetric on- and off-chip interconnects. Currently, she researches microarchitecture level optimizations for AR/VR applications.

Darya is looking for internships in the field of AR/VR related but not limited to computer architecture and machine learning algorithms.

Sonal is a assistant professor in the Department of Computer Science and Engineering at the National Institute of Technology Raipur. Prior NIT Raipur, she was postdoctoral fellow at Indian Institute of Technology (IIT) Guwahati, India from March 2018-2020. She received her M.Tech and PhD degree from the Malaviya National Institute of Technology (MNIT) Jaipur, India. Her PhD dissertation was on Exploration of Efficient Manycore Multiple Networks-on-Chip Architectures. Her research interests lie in improving energy efficiency via power-gating for multiple networks-on-chip (NoC) architectures and self-learning NoC architectures. Her thesis work awarded travel grant in DATE 2019. She is the recipient of the best paper award by TCVLSI in IEEE-SES 2018. Her PhD work is published in reputed conferences VDAT 2015, VLSI Design 2016, DAC 2019 and journals. She has received multiple recognitions, including PhD Fellowship by the Ministry of Human Resource and Development (MHRD) Govt. of India and Institute Postdoctoral Fellowship by Indian Institute of Technology Guwahati.

Currently serving as SiFive's VP of Hardware Engineering. Passionate about getting more women into the open source community. R & D interests include Chip Generators, Cryptographic Hardware, shared memory protocols, accelerating custom ASIC Design. Earned her Ph.D. in Electrical Engineering from Stanford University (w/ Prof. Mark Horowitz) and her undergraduate degree in Engineering from Brown University.