Research interests include energy-efficient computing, hardware-software co-design, near memory processing, non-volatile memory.

Hi, I am Nayana, a final year Ph.D. candidate at Princeton University, advised by Prof. David August. My research interests are in the field of computer architecture and hardware/software co-design, with more focus on performance improvement at the Datacenter scale. I interned for two consecutive summers with Google Wide Profiling team at Google. Before joining Princeton, I was working as a Verification Engineer at AMD, Bangalore, India.

I'm a PhD student researching microarchitectural security and side-channel attacks in the CoreSec group at the IAIK, Graz University of Technology. Developing microarchitectural attacks and countermeasures has exposed me to many subfields of computer architecture. I'm particularly interested in ISA design and instruction decoding, the 'conflict' between energy efficiency and security, and whether we can rearchitect the CPU and the memory subsystem to reduce this conflict.

For decades, Moore’s Law and its partner Dennard Scaling have driven technology trends that have enabled exponential performance improvements in computer systems at manageable power dissipation. With the slowing of Moore/Dennard improvements, designers have turned to a range of approaches for extending scaling of computer systems performance and power efficiency. Unfortunately, these scaling gains come at the expense of degraded hardware-software abstraction layers, increased complexity at the hardware-software interface, and increased challenges for software reliability, interoperability, and performance portability. My work explores the way forward for computer systems designers in this “Post-ISA” era of shifting abstractions. My group looks hardware and software design issues for specialization/heterogeneity and methods for formal verification. We are also increasingly focused on the hardware/software systems issues of Quantum Computing.