Angeles G. Navarro received her PhD in Computer Science from the University of Malaga (Spain) in 2000. She is a Professor in the Department of Computer Architecture at the University of Malaga. She has been a Research Visiting Scholar in the University of Illinois at Urbana-Champaign, the Technical University of Munich, the EPCC at the University of Edinburgh, the University of Bristol, and a Research Visitor in IBM T.J. Watson Research Center at New York and in Cray Inc at Seattle. She is the author or co-author of more than 80 papers and has served as a program committee member for several High Performance Computing related conferences. Her research interests are in parallel programming models and compilation techniques for heterogeneous and reconfigurable architectures.

Dr. Navarro has been involved in many initiatives to promote women in Computer Science. She is the co-founder of WSARTECO (Women in SARTECO), a community that is part of the Spanish Computer Architecture Scientific Society, which encourages junior and senior women working in the area to increase visibility and to develop a supporting network.

Darya Mikhailenko is pursuing a PhD in Electrical and Computer Engineering at the University of Rochester under the supervision of Prof. Engin Ipek. Her interests cover areas of energy-efficient computer architectures, machine learning for computer vision applications, memory management, accelerators, and architecture modeling for emerging technologies. Darya worked as a research assistant at Nanoelectronics Research Laboratory (Purdue University, U.S.A.) and Bioinspired Microelectronics Systems Laboratory (Nazarbayev University, Kazakhstan) on the implementation of brain-computer architecture to actualize deep neural networks. Her recent work was dedicated to techniques to minimize data movement energy by exploiting asymmetric on- and off-chip interconnects. Currently, she researches microarchitecture level optimizations for AR/VR applications.

Darya is looking for internships in the field of AR/VR related but not limited to computer architecture and machine learning algorithms.

Bahar Asgari is an assistant professor in the Department of Computer Science at the University of Maryland, Collage Park with a joint appointment in UMIACS. Before joining UMD in August 2022, she spent a year working at Google on its Systems and Services Infrastructure team. She received her Ph.D. in electrical and computer engineering from Georgia Tech in 2021, where she was advised by Dr. Sudhakar Yalamanchili and Dr. Hyesoon Kim. Bahar’s research interests include but are not limited to domain-specific architecture design, near memory processing, and reconfigurable computing. Her proposed low-cost hardware accelerators and hardware/software co-optimization that deal with essential challenges of sparse problems contribute to a widespread application domain from machine learning to scientific computing.

I am interested in parallel and heterogeneous architectures and application-specific accelerators, and how we can design and program them to continue improving application performance and efficiency in the face of limits to frequency and power scaling.