Hi, I am Nayana, a final year Ph.D. candidate at Princeton University, advised by Prof. David August. My research interests are in the field of computer architecture and hardware/software co-design, with more focus on performance improvement at the Datacenter scale. I interned for two consecutive summers with Google Wide Profiling team at Google. Before joining Princeton, I was working as a Verification Engineer at AMD, Bangalore, India.

Lizy Kurian John is B. N. Gafford Professor in the Electrical and Computer Engineering at UT Austin. She received her Ph. D in Computer Engineering from the Pennsylvania State University. Her research interests include workload characterization, performance evaluation, architectures with emerging memory technologies such as die-stacked DRAM, and high performance processor architectures for emerging workloads. She is recipient of NSF CAREER award, UT Austin Engineering Foundation Faculty Award, Halliburton, Brown and Root Engineering Foundation Young Faculty Award 2001, University of Texas Alumni Association (Texas Exes) Teaching Award 2004, The Pennsylvania State University Outstanding Engineering Alumnus 2011, etc. She has coauthored a book on Digital Systems Design using VHDL (Cengage Publishers, 2007, 2017), a book on Digital Systems Design using Verilog (Cengage Publishers, 2014) and has edited 4 books including a book on Computer Performance Evaluation and Benchmarking. She is in ISCA and HPCA Hall of Fame, holds 10 US patents and is a Fellow of IEEE.

I am Shivani Shah, completed my Bachelor of Technology majoring in Information and Communication Technology from School of Engineering and Applied Science, Ahmedabad University. Currently, I am Research Scholar at IIIT Banglore. During my graduation, I have done a few projects such as 'Implementation of 8-bit MIPS processor on FPGA' (Coding Language: Verilog, Tool: Xilinx). I did my final year project on designing ‘Reduced Hardware Hybrid Branch Predictor’ at Ahmedabad University. Control Block is one of the major parts of any computer architecture, I focused on designing hybrid hardware, a combination of 1-bit predictor and 2-bit predictor, but hardware only of 2-bit predictor which drastically optimized the hardware requirements without compromising processor speed. So right now I have done instruction-level parallelism.