Dr. Ghazal Tashakor is a scientific staff member affiliated with multiple institutes and universities in Germany and Spain. She obtained her Ph.D. in High-Performance Computing (HPC) and advanced simulation from the Autonomous University of Barcelona in 2019. Her ongoing research endeavors primarily focus on conducting large-scale computer simulations. Additionally, she serves as a core developer in distributed and parallel architecture patterns, ranging from grid computing to data visualization/monitoring, with a specific emphasis on Big Data and advanced hierarchical models. She collaborates with various research centers in Germany, including Fraunhofer and Jülich Supercomputer Centre.

Computer Science Engineer, specializing in Hardware and Network Systems from SUNY Buffalo. Highly passionate about Research in the field of VLSI , Computer Architecture and Hardware Security. Also, I have a great interest in the field of Routers and Switches, MIMO technology and VLSI Digital Circuit designing. Along with my Master's I am also working as a Graduate Assistant in HPVSA Laboratory, in the Dept. of Computer Science Engineering , SUNY Buffalo. My current research is on design and optimization of Physically Unclonable Functions (PUF), which could act as a fingerprint for semiconductor devices.

Furthermore, I have obtained my Bachelor's degree in Electronics and Communication Engineering from SRMIST,Chennai,India. During my undergrad I sincerely worked under my Professor for the research project - on Tunnel Field Effect Transistor, which we presented at the National Conference Silicon'18. Our paper "Design Optimization of Tunnel Field Effect Transistor" was published in International Journal of Recent Technology and Engineering (IJRTE) in March 2019.

The amalgamation of Electronics, Computers and Communications have helped me to pave stronger base for the skills needed in the field of Computer Hardware and Computer Networks.

Yasuko Eckert is a Sr. Member of Technical Staff at AMD Research and an IEEE Senior Member. She received her M.S. and Ph.D. from the University of Wisconsin-Madison in 2007 and 2011, respectively. She received her B.S. from the University of Texas at Austin in 2004. Her research interests include SoC- and package-level architectural optimizations, 3D integration, energy-efficient computing, and microarchitecture designs. She is currently serving as the Tutorial/Workshop Co-chair of the 51st International Symposium on Microarchitecture, as well as an Associate Editor of IEEE Transactions on Multi-Scale Computing Systems (TMSCS). She has served on the Technical Program Committees of MICRO, HPCA, PACT, ISLPED, and ICCD. She holds more than 25 U.S. patents.