Reetu Das is an Assistant Professor at University of Michigan. Prior to this, she was a research scientist at Intel Labs, and the researcher-in-residence for the Center for Future Architectures Research. She received her PhD in Computer Science and Engineering from Pennsylvania State University, University Park. Some of her recent projects include in-memory architectures, fine-grain heterogeneous core architectures for mobile systems, and low-power scalable interconnects for kilo-core processors. Her research program has been funded by National Science Foundation, the Center for Future Architectures Research (C-FAR), Semiconductor Research Corporation and Intel Corporation. Reetu is an expert in computer architecture. She has authored over 45 papers, filed 7 patents and served on over 20 technical program committees. She has served as a track chair for Design Automation Conference for two consecutive years. Her research has been recognized by several awards. She has received outstanding research and teaching assistantship awards at Pennsylvania State University, an IEEE Top Picks award, an NSF CAREER award, CRA-W Borg Early Career Award, IEEE/ACM MICRO Hall of Fame award and was recently inducted to ISCA Hall of Fame. Her recent work on in-memory design named Compute Caches received the best Demo award in C-FAR and was selected from 50 projects from leading University research groups. She also serves as the CEO of a precision medicine start-up, Sequal Inc.

I am a Ph.D. candidate at Carnegie Mellon University, advised by Prof. Onur Mutlu and Prof. Phil Gibbons. My research focuses on the interaction between programming models, system software, and hardware architecture, and explores how richer cross-layer abstractions can enhance performance, programmability, and portability. I am excited about rethinking the roles played by different levels of the stack in the modern era of rapidly evolving, specialized, and data-centric computing landscapes. During my Ph.D., I have been fortunate to intern at Microsoft Research, Nvidia Research, and Intel Labs. I am currently a visiting student at ETH Zurich.

My main research focus is in hardware accelerators, especially FPGAs. I have done research in floating point implementations, unsupervised learning, medical imaging, and privacy preserving data processing. At Northeastern I am head of the Reconfigurable Computing Laboratory and a member of the Computer Engineering group. Throughout my career, I have been funded by both government agencies and companies, including AMD, DARPA, NSF, Google, and MathWorks. I am the recipient of a Fulbright Scholar Award and a Charter Member of the IEEE Computer Society Distinguished Contributor Recognition Program. My current research focus is on FPGAs in the data center and FPGAs directly attached to the network.

Evey Liu recently finished her undergraduate study at the University of Waterloo for Computer Engineering. She will begin graduate school at the University of Toronto with supervisor Natalie Enright Jerger in January 2019. She is passionate about generic computer architecture and is open to explore different specializations within the field.