I am a PhD student in the School of Electrical and Computer Engineering at Purdue University. I received my Bachelors (2018) in Electronics and Communication Engineering (with honors) from Indian Institute of Technology Roorkee, India. I was a recipient of the IITR Heritage Excellence Award, INSA-NASI-IASc Summer Research Fellowship, and ENCORE Scholarship Award for outstanding performance in academics and curricular during my time at IIT Roorkee. Subsequently, I worked for Texas Instruments for one year on standard cell design and methodologies in collaboration in EDA team. I joined my PhD program in Fall 2019 and since have been a part of Nanoelectronics Research Lab. My research interests include computer architecture, hardware accelerators for Machine Learning applications using emerging technologies, and design of processing in/near memory based architectures. In my free time, I like to play badminton, dance, go for running, or listen to music.

Dr. Ghazal Tashakor is a scientific staff member affiliated with multiple institutes and universities in Germany and Spain. She obtained her Ph.D. in High-Performance Computing (HPC) and advanced simulation from the Autonomous University of Barcelona in 2019. Her ongoing research endeavors primarily focus on conducting large-scale computer simulations. Additionally, she serves as a core developer in distributed and parallel architecture patterns, ranging from grid computing to data visualization/monitoring, with a specific emphasis on Big Data and advanced hierarchical models. She collaborates with various research centers in Germany, including Fraunhofer and Jülich Supercomputer Centre.

Server memory management is an evolving and challenging area. With growing memory capacity installed per machine and increasing memory DIMM costs, data center planners are facing with huge increase in memory TCO. A plausible direction is to categorize memory accesses by required service level objective (SLO) with the end goal to map lower SLO request to cheaper but low quality memory resource, while using expensive, highest quality memory resource for most critical application request. I work in Linux server memory management to categorize memory access transparent to the user space.

For decades, Moore’s Law and its partner Dennard Scaling have driven technology trends that have enabled exponential performance improvements in computer systems at manageable power dissipation. With the slowing of Moore/Dennard improvements, designers have turned to a range of approaches for extending scaling of computer systems performance and power efficiency. Unfortunately, these scaling gains come at the expense of degraded hardware-software abstraction layers, increased complexity at the hardware-software interface, and increased challenges for software reliability, interoperability, and performance portability. My work explores the way forward for computer systems designers in this “Post-ISA” era of shifting abstractions. My group looks hardware and software design issues for specialization/heterogeneity and methods for formal verification. We are also increasingly focused on the hardware/software systems issues of Quantum Computing.