Currently serving as SiFive's VP of Hardware Engineering. Passionate about getting more women into the open source community. R & D interests include Chip Generators, Cryptographic Hardware, shared memory protocols, accelerating custom ASIC Design. Earned her Ph.D. in Electrical Engineering from Stanford University (w/ Prof. Mark Horowitz) and her undergraduate degree in Engineering from Brown University.

Martha Kim is an Associate Professor of Computer Science at Columbia University where she leads the ARCADE Lab. Kim's research interests are in computer architecture, parallel programming, compilers, and low-power computing. Her work has explored low-cost chip manufacturing systems, reconfigurable communication networks, and fine-grained parallel application profiling techniques. Her current research focuses on hardware and software techniques to improve the usability of hardware accelerators as well as data-centric accelerator design. Kim holds a PhD in Computer Science and Engineering from the University of Washington and a bachelors in Computer Science from Harvard University. She is the recipient of the 2013 Rodriguez Family Award, the 2015 Edward and Carole Kim Faculty Involvement Award, a 2013 NSF CAREER award, and the 2016 Anita Borg Early Career Award.

For decades, Moore’s Law and its partner Dennard Scaling have driven technology trends that have enabled exponential performance improvements in computer systems at manageable power dissipation. With the slowing of Moore/Dennard improvements, designers have turned to a range of approaches for extending scaling of computer systems performance and power efficiency. Unfortunately, these scaling gains come at the expense of degraded hardware-software abstraction layers, increased complexity at the hardware-software interface, and increased challenges for software reliability, interoperability, and performance portability. My work explores the way forward for computer systems designers in this “Post-ISA” era of shifting abstractions. My group looks hardware and software design issues for specialization/heterogeneity and methods for formal verification. We are also increasingly focused on the hardware/software systems issues of Quantum Computing.

Thesis Title: LongLiveNoC: Wear Levelling, Write Reduction and Selective VC allocation for Long lasting Dark Silicon aware NoC Interconnects

Increasing processing demand has led to the development of chip multiprocessors which can have multiple to many cores connected with each other and with the on-chip caches. These connections are established by an on-chip packet-switched Network-on-Chip (NoC). Scaling of technology nodes increases the power dissipated by the chips leading to thermal restrictions. To control the chip thermal design power, certain components (like cores and caches) may be turned off. However, in this scenario of dark silicon, the interconnect is expected to be available.

The thesis aims to save power consumed by this always ON interconnect by replacing the power-hungry SRAM buffers in the routers with low leakage Non-Volatile Memory (NVM) based buffers. However, the major challenges with the employment of the NVMs are slower writes and weak write endurance.

The thesis proposes:
1. Methods to evenly distribute the writes across these NVM buffers in order to increase their lifetime. This is done by static and dynamic allocation of buffers to the virtual channels and their selection during packet transmission.

2. Power can also be saved by using frequency scaling of the routers and/or turning off certain buffers when the usage is less. The investigation is done for all such approaches and power savings are demonstrated.

3. Endurance can be improved and energy can be saved if we can reduce the number of writes performed on the buffers. This is achieved by proposing two compression techniques leading to reduced network traffic and improved lifetime.

All the above methods help in improving the lifetime of the NVM based NoC interconnects in the context of dark silicon.