Call for Papers: IEEE Micro Special Issue on Ultra-low-power Processors

IEEE Micro Special Issue on Ultra-low-power Processors

Guest Editors:
David Brooks, Harvard University
John Sartori, University of Minnesota

– Submissions due: April 29, 2017
– Author notification: June 17, 2017
– Revised papers due: July 15, 2017
– Final versions due: August 19, 2017
– Publication: November/December 2017

Emerging applications for connected sensing and wearable computing create robust demand for ultra-low-power (ULP) edge computing devices and associated system-on-chip (SoC) architectures. In fact, the ubiquity of ULP processing has already made such embedded devices the highest volume processor part in production, with an even greater dominance expected in the very near future. Emerging applications like the internet of everything are calling for a processor embedded in every object, and the number of processors is projected to be in the billions or trillions. At the same time, the explosion of data generated from these devices, in conjunction with the traditional model of using cloud-based services to process the data, places tremendous demands on limited wireless spectrum and energy-hungry wireless networks. Smart, ultra-low-power edge devices are the only viable option that can meet these demands.

This special issue of IEEE Micro will explore novel design techniques for ultra-low-power processors, bridging the gap between VLSI/CAD, microarchitecture, and lower levels of the compute stack, in the context of emerging applications that are driving the ultra-low-power revolution.

Areas of interest for this issue include the following.
– Application-aware design and optimization of ULP processors
– VLSI, CAD, and microarchitecture techniques for ULP processors
– Studies of new device technologies (e.g. TFETs) applied to ULP processors
– Energy harvesting approaches in conjunction with ULP processing
– Power reduction techniques for end-to-end ULP systems, including techniques that target communication costs with smarter edge computation

Log in to ScholarOne Manuscripts and submit your manuscript. Acceptable file formats are Microsoft Word document and PDF. Please direct ScholarOne questions to the IEEE Micro magazine assistant ( Manuscripts should not exceed 5,000 words, including a maximum of 12 references, with each average-­sized figure counting as 250 words. Please include all figures and tables, as well as a cover page with author contact information (name, postal address, phone, fax, and email address) and a 200­-word abstract. Accepted articles will be edited for structure, style, clarity, and readability. For more information, please visit the IEEE Micro author guidelines. Submitted manuscripts must not have been previously published or submitted for publication elsewhere, and all manuscripts must be cleared for publication. All conference papers must have at least 30 percent new content compared to the original.

Contact the guest editors at, or the EiC at

Call for Applications: The 2017 CRA-W Grad Cohort Workshop

The 2017 CRA-W Grad Cohort Workshop
Washington DC, USA
April 7-8, 2017.

Applications due: November 30, 2016

The CRA-W Grad Cohort program, initiated in 2004, is generously funded by sponsors from industry, ACM, CRA, academia, the National Science Foundation, and the computing community. Grad Cohort aims to increase the ranks of senior women in computing-related studies and research by building and mentoring nationwide communities of women through their graduate studies.

The Grad Cohort Workshop welcomes women graduate students in their first three years of graduate school into the community of computing researchers and professionals. Participants will meet for two days with 20 to 25 senior computing-related researchers and professionals, who will share pertinent information on graduate school survival skills, as well as more personal information and insights about their experiences. The rewards of a research career will be emphasized. The workshop will include a mix of formal presentations and informal discussions and social events. Through this workshop, students will be able to build mentoring relationships and develop peer networks that will form the basis for ongoing activities during their graduate careers.

Reasonable travel expenses, meals, and lodging will be provided for students chosen to participate in this program.

The Grad Cohort 2017 application is now open. Applications are due November 30th. Full details at the event web site.

For questions about the Grad Cohort program, please write to

Call for Papers: Computing Frontiers 2017

ACM International Conference on Computing Frontiers (CF’17)
Siena, Italy
May 15 – 17, 2017,

Submissions deadline: January 20, 2017
Notification: March 14, 2017
Camera-Copy Papers Due: April 4, 2017
Conference Dates: May 15 – 17, 2017

The next ACM International Conference on Computing Frontiers will be held May 15-17 in Siena, Italy. Computing Frontiers is an eclectic, collaborative community of researchers who investigate emerging technologies in the broad field of computing: our common goal is to drive the scientific breakthroughs that transform society. Technology is experiencing revolutions in memory devices and systems, networks, electronic device production, machine learning, data analytics, cloud computing, techniques to improve power and energy efficiency, systems portability/wearability, to name but a few areas. New application domains that affect everyday life are emerging, especially in this era of highly interconnected and collaborative cyber-physical systems. Boundaries between the state-of-the-art and revolutionary innovation constitute the frontiers that mark the advances of science, engineering, and information technology.

Early research that envisions future technologies provides the bases that allow novel materials, devices, and systems to become mainstream. Collaborative efforts among researchers with different expertises and backgrounds enables revolutionary scientific breakthroughs that lead to innovative solutions over a wide spectrum of computer systems, from embedded and hand-held/wearable devices to supercomputers and data centers.

We seek original research contributions at the frontiers of a wide range of topics, including novel computing paradigms, computational models, algorithms, application paradigms, development environments, compilers, operating environments, computer architecture, hardware substrates, memory technologies, and smarter life applications:

– Algorithms and Models of Computing: Approximate and inexact computing, quantum and probabilistic computing
– Biological Computing Models: Brain computing, neural computing, computational neuroscience, biologically-inspired architectures
– Limits on Technology Scaling and Moore’s Law: Defect- and variability-tolerant designs, graphene and other novel materials, nanoscale design, optoelectronics, dark silicon
– Uses of Technology Scaling: 3D stacked technology, challenges of many-core designs, accelerators, PCM’s, novel memory architectures, mobile devices
– Embedded and Cyber-Physical Systems: Design space exploration, modeling and development frameworks for interconnected systems and CPS and CPSoS, ultra-low power designs, energy scavenging, reactive and real-time systems, reconfigurable and self-aware systems, sensor networks and internet of things, and architectural innovation for wearable computing
– Big Data Analytics: High performance data analytics, data search and representation, architecture, and system design
– Machine and Deep Learning: innovative algorithms and architectures, neuromorphic approaches
– Large-Scale System Design: Homogeneous and heterogeneous architectures, runtimes, networking technologies and protocols, power- and energy-management for cloud and grid systems, data centers, exa-scale computing
– Compiler Technologies: Advanced/novel analyses, hardware/software integrated solutions, domain-specific languages, high-level synthesis
– Security: Methods, system support, and hardware for protecting against malicious code; real-time implementations of security algorithms and protocols; quantum and post-quantum cryptography; advanced persistent threats, cyber and physical attacks, and countermeasures
– Computers and Society: Education, health, cost/energy-efficient design, smart cities, and emerging markets
– Interdisciplinary Applications: Applications bridging multiple disciplines in interesting ways

We also strongly encourage submissions in emerging fields that may not fit into traditional categories. If in doubt, please contact the PC co-chairs by email.

Authors are invited to submit full papers, position papers, trend papers, and poster abstracts to the main conference. Authors must declare in advance to which category they are submitting. Full papers are a maximum of eight (8) double-column pages in ACM conference format. Authors may purchase up to two (2) additional pages at 100 Euro per page. Authors can submit full papers of up to 10 double-column pages, provided that they agree to pay for the additional pages if the paper is accepted. All other types of submissions should be at least two (2) pages and not more than four (4) pages in the same format. These limits include figures, tables, and references. Our review process is double-blind: please remove all identifying information from the paper submission (and cite your own work in the third person). Authors of interesting work not mature enough for an oral presentation may be offered the option of presenting their work as posters.

Position papers, trend papers, poster abstracts and workshop papers will be published in the proceedings and in the ACM Digital Library. As per ACM guidelines, at least one unique author of each accepted paper is required to register for the conference.

Selected papers from the Computing Frontiers 2017 conference will be invited to extend their work for publication in a special issue of the Springer Journal of Signal Processing Systems (JSPS).

General Chair:
Roberto Giorgi, University of Siena, IT

Program Co-Chairs:
Michela Becchi, University of Missouri, US
Francesca Palumbo, University of Sassari, IT

Call for Papers: Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems

2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems (AISTECS)
in conjunction with HiPEAC 2017
Stockholm, Sweden
January 25, 2017

Submission deadline: October 30, 2016
Author notification: November 15, 2016
Camera-ready papers due: November 30, 2016

The AISTECS workshop promotes research and knowledge exchange on evolutionary as well as revolutionary interconnect technologies. This includes interconnect-related topics in the perspective of their adoption in future high performance systems and, in general, within future computing systems from servers/workstations down to embedded devices and the Internet of Things, which are tied to strict power budget and thermal envelopes because of the impending green computing era. To this end, the exploration of emerging interconnect technologies along with the design of disruptive/novel ideas at the microarchitectural network level are necessary, both leading to crucial challenges and interesting design tradeoffs for their widespread adoption in next-generation computing platforms. Furthermore, we expect that novel interconnect features have the potential to constitute disruptive new ideas able to modify the expected shape of future computer systems from the design point of view and also from the programmability and/or runtime management perspectives. Finally the workshop aims to increase the synergy to develop advanced interconnect solutions and technologies for emerging computing systems from a complete range of perspectives following a holistic approach: from raw technology issues and solutions up to studies at the overall system level of modern multi-/many-core systems. This encompasses novel network solutions from both academic and industrial researchers.

Workshop Topics:
– Networks on Chip (NoCs)
– Network architectures (topology, control-flow, routing, etc.)
– Silicon Photonics and Optical NoCs
– Interconnect solutions for heterogeneous GPU/FPGA-based multi/macro-chip systems
– Communication infrastructures for HPC systems, Supercomputers and Data Centers
– Emerging interconnect technologies (EIT): photonics, carbon nanotubes, through-silicon, RF, wireless NoC.
– Crucial challenges and design tradeoffs for EIT in future computer systems
– Low-level technological improvements and implications of EIT in future communication systems
– Thermal-/energy-and power-related NoC optimization and dark silicon
– Reconfigurable/programmable interconnect components
– Efficient interconnect for 2.5D and 3D packaging
– Asynchronous interconnect designs
– Clockless interconnects with focus on automation of their design methodology
– Network infrastructures for Internet-of-Things devices
– Architectures for QoS support and coherency
– Network solutions for performance isolation in many-core systems
– Impact of the interconnect on application performance
– Reliability, availability, fault tolerance for system communication
– Programming models for communication-centric systems
– Secure interconnection networks for intra-chip and inter-chip communication
– Efficient memory networks for large-scale workloads and Big Data applications

We invite contributions of previously unpublished results on the listed areas of future interconnect-centric systems, although not limited to them. We are interested in research, experimental, systems-related, survey, perspective and work-in-progress papers in all aspects of interconnects in general and emerging interconnect technologies/paradigms in particular at all levels of development.

Papers must be in PDF format and should include title, authors and affiliations as well as the e-mail address of the contact author. Papers must be formatted in accordance to the ACM two-column style. ACM Word or LaTeX style templates will be available on the website. Submissions must be limited to 4 pages. Papers deviating significantly from the paper size and formatting rules may be rejected without review.

Accepted papers will be published in the ACM Digital Library within the ACM International Conference Proceedings Series (ICPS). Authors will be sent the ACM form and instructions to finalize the camera-ready submission and to complete the publication procedure.

General Chairs:
– Sören Sonntag (Intel, Germany)
– José Manuel Garcia Carrasco (University of Murcia, Spain)

Program Chairs:
– José Luis Abellán Miguel (Catholic University of Murcia, Spain)
– Daniel Müller-Gritschneder (TU Munich, Germany)

Publication and Web Chair:
– Marco Balboni (University of Ferrara, Italy)

Steering Committee:
– Davide Bertozzi (University of Ferrara, Italy)
– Cyriel Minkenberg (Rockley Photonics, Switzerland)

Technical Program Committee:
– Sergi Abadal, Universitat Politècnica de Catalunya, Spain
– Federico Angiolini, iNoCS, Switzerland
– José Luis Ayala, Complutense University of Madrid, Spain
– Sandro Bartolini, University of Siena, Italy
– Giorgios Dimitrakopoulos, Democritus University of Thrace, Greece
– Holger Fröning, University of Heidelberg, Germany
– Francisco Gilabert, Intel, Germany
– Ajay Joshi, Boston University, USA
– David Kaeli, Northeastern University, USA
– John Kim, KAIST, South Korea
– Sébastien Le Beux, Lyon Institute of Nanotechnology (INL), France
– Sergei Mingaleev, VPIphotonics, Germany
– Chrysostomos Nicopoulos, University of Cyprus
– Sébastien Rumley, Columbia University, USA
– Jose Luis Sanchez Garcia, University of Castilla-La Mancha, Spain
– Laurent Schares, IBM, USA
– Johana Sepúlveda, TU Munich, Germany
– Federico Silla, Universitat Politécnica de Valencia, Spain
– Eitan Zahavi, Mellanox, Israel

Call for Workshops and Tutorials: PLDI 2017

2017 ACM Conference on Programming Language Design and Implementation (PLDI)
Barcelona, Spain
June 19-23, 2017

Proposals for workshops with proceedings due: Nov 28, 2016
Acceptance Notification: Dec 9, 2016
Proposals for workshops/tutorials without proceedings due: Jan 30, 2017
Workshop and Tutorials held (tentatively): Jun 18,22,23 2017

PLDI 2017 will host co-located workshops and tutorials for which it calls for proposals. This year, PLDI is a part of a large cluster of co-located conferences including ECOOP, Curry On, LCTES, ISMM, DEBS and others. Take your chance in addressing the diverse audience of the premier forum in programming language design and implementation by proposing your event. PLDI welcomes prominent events focusing on programming language design theory and practice, for which it can provide guidance in publishing results in the ACM Digital Library.


A proposal should provide:
– Name of the workshop/tutorial.
– Duration of the workshop/tutorial.
– Organizers: names, affiliation, contact information, brief (100 words) biography.
– A short description (150-200 words) of the topic.
– Event format: workshop/tutorial; type of submissions if any; review process; results dissemination; references to previous events.
– Expected attendance and target audience within PLDI community.

Please submit proposals in plain text to Aaron Smith . Workshops that would like their proceedings included in the ACM Digital Library must submit a proposal by November 28. Proposals for co-located workshops/tutorials without formal proceedings will be accepted until January 30.

General Chair: Albert Cohen, INRIA, France
Program Chair: Martin Vechev, ETH Zurich, Switzerland

Call for Papers: Workshop on Accelerators and Hybrid Exascale Systems

The Seventh International Workshop on Accelerators and Hybrid Exascale Systems (AsHES)
in conjunction with IPDPS’17
Orlando, Florida, USA
May 29, 2017

Paper Submission: Jan. 13, 2017 (AoE)
Paper Notification: Feb. 15, 2017
Camera-Ready: Feb. 25, 2017

Current and emerging systems are deployed with heterogeneous architectures and accelerators of more than one type (e.g., GPGPU, Intel® Xeon Phi™, FPGA) along with hybrid processors of both lightweight and heavyweight cores (e.g., APU, big.LITTLE). Such architectures also comprise hybrid memory systems equipped with stacked/hierarchical memory and non-volatile memory in addition to regular DRAM. Programming such a system can be a real challenge along with locality,
scheduling, load balancing, concurrency and so on.

This workshop focuses on understanding the implications of accelerators and heterogeneous designs on the hardware systems, porting applications, performing compiler optimizations, and developing programming environments for current and emerging systems. It seeks to ground accelerator research through studies of application kernels or whole applications on such systems, as well as tools and libraries that improve the performance and productivity of applications on these systems. The goal of the workshop is to bring together researchers and practitioners who are involved in application studies for accelerators and other heterogeneous systems, to learn the opportunities and challenges in future design trends for HPC applications and systems.

Topics of interest for workshop submissions include (but are not limited to):
– Strategies for programming heterogeneous systems using high-level models such as OpenMP and OpenACC, and low-level models such as OpenCL, CUDA;
– Methods and tools to tackle challenges in scientific computing at extreme scale;
– Strategies for application behavior characterization and performance optimization for accelerators;
– Techniques for optimizing kernels for execution on GPGPU, Intel Xeon Phi and future heterogeneous platforms;
– Models of application performance on heterogeneous and accelerated HPC systems;
– Compiler Optimizations and tuning heterogeneous systems including parallelization, loop transformation, locality optimizations, Vectorization;
– Implications of workload characterization in heterogeneous and accelerated architecture design;
– Benchmarking and performance evaluation for accelerators;
– Tools and techniques to address both performance and correctness to assist application development for accelerators and heterogeneous processors;
– System software techniques to abstract application domain-specific functionalities for accelerators;

Keynote Speaker:
Tim Mattson (Intel) will give a keynote speech at AsHES 2017.

Papers should present original research and should provide sufficient background material to make them accessible to the broader community. Submitted manuscripts may not exceed 10 single-spaced double-column pages using 10-point size font on 8.5×11 inch pages (IEEE conference style), including figures, tables, and references. See the style templates for latex or word for details.

Submissions will be judged based on relevance, significance, originality, correctness and clarity.
Submission site:

The proceedings of this workshop will be published electronically together with IPDPS proceedings via the IEEE Xplore Digital Library.

General Chair:
Sunita Chandrasekaran, University of Delaware, USA

Program Co-Chairs:
Antonio J. Peña, Barcelona Supercomputing Center, Spain
Sangmin Seo, Argonne National Laboratory, USA

Program Committee:
Ashwin Aji, AMD, USA
James Beyer, NVIDIA Corporation, USA
Huimin Cui, Institute of Computing Technology, CAS
Anthony Danalis, University of Tennessee, USA
Khaled Hamidouche, The Ohio State University, USA
Jeff Hammond, Intel Labs, USA
Siva Kumar Sastry Hari, NVIDIA Corporation, USA
Hennry Jin, NASA, USA
Guido Juckeland, HZDR, Germany
Sriram Krishnamoorthy, Pacific Northwest National Laboratory, USA
Seyong Lee, Oak Ridge National Laboratories, USA
Dong Li, University of Calfornia, Merced, USA
John Lidel, Texas Tech University, USA
Piotr Luszczek, University of Tennessee, USA
Naoya Maruyama, RIKEN AICS, Japan
Stephen Olivier, Sandia Nationl Lab, USA
Kelly Shaw, University of Richmond, USA
Xipeng Shen, North Carolina State University, USA
Min Si, Argonne National Laboratory, USA
Bronis de Supinski, Lawrence Livermore National Laboratory, USA
Hao Wang, Virginia Tech, USA
Yongpeng Zhang, Stone Ridge Technology, USA

Steering Committee:
Pavan Balaji, Argonne National Laboratory, USA
Yunquan Zhang, Chinese Academy of Sciences, China
Satoshi Matsuoka, Tokyo Institute of Technology, Japan
Jiayuan Meng, Argonne National Laboratory, USA
Xiaosong Ma, Qatar Computing Research Institute, Qatar
Barbara Chapman, University of Houston, USA
Guang R. Gao, University of Delaware, USA
Xinmin Tian, Intel, USA
Michael Wong, IBM, Canada
James Dinan, Intel Corporation

Please send any queries about the AsHES workshop to

Call for Submissions: Intel Hardware Accelerator Research Program v2

Submission Deadline: Oct 21, 2016

Intel Corporation is pleased to announce the second round of the Hardware Accelerator Research Program, which will provide faculty with access to computer systems containing Intel microprocessors and an Altera Arria-10 FPGA in a multi-chip package (MCP) that incorporates Intel’s Accelerator Abstraction Layer Software in order to spur research in programming tools, operating systems, and innovative applications for accelerator-based computing systems.

In recent years, accelerators and coprocessors have attracted a great deal of interest, but the effort required to program heterogeneous systems has limited their impact. Current programming tools for these technologies require a great deal of domain-specific knowledge to reformulate algorithms for FPGA, partition a design between FPGA and CPU, and orchestrate data transfers between FPGA and CPU. In addition, portability still remains a challenge between different CPU+FPGA systems.

In order to improve the usability of these systems, Intel Corporation is interested in research into tools, applications, and methodologies that:
– Reduce the amount of effort required to map an application onto a coprocessor or accelerator
– Operating systems and schedulers that can automatically assign tasks to the most efficient hardware in a heterogeneous system
– Techniques to make applications portable across different hardware technologies
– Innovative applications that demonstrate the potential of heterogeneous systems.

To support and encourage this research, the Hardware Accelerator Research Program is making systems available to researchers that pair a 12-core Intel microprocessor with an Altera Arria10 FPGA.
Intel plans to build approximately 30 next-generation Hardware Accelerator Research Program systems (Broadwell + Arria10). These systems will be provided through two allocations:
1. To enable distributed-systems and data-center research, systems will be placed in centralized cluster installations in the U.S. and Europe (20 nodes total, 10 nodes per installation). The clusters will be made available via remote access to eligible program participants.
2. Several systems will be provided to researchers who need physical access to the platform based on their research agenda.

Researchers awarded access to Hardware Accelerator Research Program systems may also qualify for a license to use the Altera Quartus Design Software and other software tools free of charge.

Additionally, researchers awarded access to Hardware Accelerator Research Program systems will be invited to a series of workshops to be held at Intel campuses. The first workshop, to be held in late 2016 and will include tutorials on Intel’s Accelerator Abstraction Layer Software and provide basic training on how to develop hardware/software for the system. It will also give researchers an opportunity to discuss ideas for research using the Hardware Accelerator Research Program systems. Later workshops will provide a forum for researchers to present the results of their work and discuss opportunities for technology transfer with Intel researchers and product designers.

Topics of interest to this CFP include, but are not limited to:
1) Applications and algorithms, e.g.
– Studies of algorithm/application/library design, remapping, and tuning to exploit different aspects of the Hardware Accelerator Research Program MCP system, with a special focus on leveraging close accelerator coupling, cache coherency, and partial reconfiguration and the Accelerator Abstraction Layer
– Techniques to evaluate the applicability and efficiency of algorithms on different components of a reconfigurable heterogeneous architecture and to select the most effective hardware for different phases of an application
– Approaches to simplify and partially automate design, development, deployment, and/or performance characterization of applications to closely-coupled heterogeneous systems

2) Operating system integration and data center scaling, e.g.
– Operating system integration and scheduling techniques for dynamically reconfigurable accelerator-based systems, including shared access, virtualization, and migration of workloads
– Scaling approaches for cluster-level deployments of heterogeneous systems, including orchestration frameworks leveraging the platform’s re-configurability and the Accelerator Abstraction Layer’s service-oriented architecture

3) Domain-specific languages and high-level design, e.g.
– Languages and libraries for coprocessor and accelerator design and development, including domain-specific languages and other high-level design methods
– Analysis of domain- or language-specific characteristics that map to the Hardware Accelerator Research Program platform’s characteristics (i.e. partial re-configurability, close accelerator coupling, cache-coherent memory model).
– Automated HW/SW partitioning approaches that exploit the benefits of low-latency cache-coherent communication between CPU and accelerators

We welcome research proposals from academic institutions new to the program. At the same time, we specifically encourage participants in the first round of Hardware Accelerator Research Program to submit research proposals that build upon and extend the research performed within that program.

We also welcome and encourage applicants to include ideas on how to integrate reconfigurable heterogeneous platforms into their coursework/curriculum alongside their scientific research proposals.

To be eligible for this program, proposers must be associated with a non-profit college, university, or research institution. U.S. export regulations prohibit the export of goods and services to Cuba, Iran, North Korea, Sudan and Syria. Therefore, residents or nationals of these countries are not eligible to participate. Proposer and their institution must not be listed on a denial order published by the U.S. Government or any other applicable Government. We welcome proposals from individual researchers, groups, and centers. As part of our evaluation of submitted proposals, we will decide whether successful proposals will be awarded access to the cluster installations closest to their location, or whether successful proposals will receive a single Hardware Accelerator Research Program system.

Proposals will be evaluated on technical merit, potential impact of the proposed research, the proposer’s ability to carry out the proposed research, and potential for collaboration with Intel researchers. Submitters of successful proposals will be expected to sign an agreement not to resell the donated equipment for a period of three years, to make results of their work available to Intel, and to participate on the program’s web forum by giving feedback about their experiences with the Hardware Accelerator Research Program platforms.

Each Recipient must acknowledge that donated equipment is subject to export controls under U.S. and other applicable Government laws and regulations. Recipient will comply with these laws and regulations governing export, re-export, import, transfer, distribution, use, and servicing of donated equipment, and agree to obtain all required Government authorizations. Recipient will not sell or transfer donated equipment to any entity listed on a denial order published by Government, or a country subject to sanctions, without first obtaining a license or authorization. Recipient will not use, sell, or transfer donated equipment for purposes prohibited by Government, including, without limitation, the development, design, manufacture, or production of nuclear, missile, chemical or biological weapons, unless authorized by a specific license. For more details on your export obligations, please visit

Interested parties should submit a proposal of at most two 8.5″x11″ pages, in at least 10pt font, to by midnight Pacific Standard Time (UTC-8) on October 21, 2016. Proposals should be in PDF format, and should include the name and institution of the individual(s) requesting the platform, a description of the research that will be performed using the platform, and a brief summary of the requestor’s relevant previous work, if any.

Call for Participation: Tutorial on Quantum Computing

Tutorial: From Quantum Bits to Quantum Computing
in conjunction with HPCA
Austin, USA
February 5, 2017

Quantum computers hold the promise for solving efficiently important problems in computational sciences that are intractable nowadays by exploiting quantum phenomena such are superposition and entanglement. One of the most famous examples is the factorization of large numbers using Shor’s algorithm. For instance, a 2000-bit number could be decomposed in a bit more than one day using a quantum computer whereas a data center of approx. 400.000 Km2 built with the fastest today’s supercomputer would require around 100 years.

This tutorial will introduce the basic notions of quantum computing and will address the main challenges when building a large-scale quantum computer. The tutorial will provide hands-on exercises based on the QX simulator platform and will allow participants to understand what quantum circuits and quantum gates are.

-Overview of quantum computing, as compared to classical computing
-Universal quantum gates and quantum circuits
-Quantum error correction
-Quantum computer architecture
-Exercises writing small quantum circuits using the QX simulation platform

Koen Bertels, Delft University of Technology, NL
Carmen G. Almudever, Delft University of Technology, NL

Call for Presentations: Systems Support for Big Data Applications

Systems Support for Big Data Applications
in conjuction with HiPEAC Autumn Computing Systems Week
Dublin, Ireland
November 7, 2016

Submission Deadline: October 21, 2016.

We are now living in a world of Big Data. The ability to process and analyse large data sets is revolutionising the way we live, work and socialise. Building software and hardware systems that can process big data with high throughput is thus a critical task for the research community and industry. Hardware and software solutions to address the problem of how to program, optimise and manage Big Data applications form the core topic of this session.

Topics of interest for this session include, but are not limited to, recent results and demonstrations, involving:
– Novel hardware systems for data intensive applications
– Programming languages and models for Big Data applications
– Compilers and tools for Big Data optimisation
– Runtime and operating systems for Big Data applications
– Middleware and software architecture for Big Data
– Big Data applications

If you are interested in giving a presentation, send an email to Vicent Sanz Marco ( and Pavlos Petoumenos ( with a 200-word abstract by Friday, 21st of October, 2016.

Talks from industrial partners are particularly welcome.

Call for Papers: ARCS 2017

30th International Conference on Architecture of Computing Systems (ARCS 2017)
Vienna, Austria
April 3-6, 2017

Paper submission deadline: October 28, 2016
Workshop and tutorial proposals: November 30, 2016
Notification of acceptance: December 21, 2016
Camera-ready papers: January 11, 2017

The ARCS conferences series has over 30 years of tradition reporting leading edge research in computer architecture and operating systems. The focus of the 2017 conference will be on Heterogeneous Node Architectures with Deep Memory Systems. ARCS 2017 will be organized by the Complang Group at the Vienna University of Technology and the CAPP group at the Karlsruhe Institute of Technology (KIT).

Authors are invited to submit original, unpublished research papers on one or more of the following topics:
– Multi-/many-core architectures, memory systems, and interconnect networks
– Programming models, runtime systems, and middleware support for many-core and/or heterogeneous computing platforms
– Tool support for performance optimization, debugging, and verification
– Generic and application-specific architectures such as reconfigurable systems in hardware and software
– Robust and fault-tolerant systems structures
– Architectures and design methods/tools for real-time embedded systems
– Cyber-physical systems and distributed computing architectures
– Organic and autonomic computing including both theoretical and practical results on self-organization, self-configuration, self-optimization, self-healing, and self-protection techniques
– Operating Systems, including but not limited to scheduling, memory management, power management, and real-time OS (RTOS) concepts
– Energy and power-aware computing, including green computing topics
– System aspects of ubiquitous and pervasive computing such as sensor nodes, novel input/output devices, novel computing platforms, architecture modeling, and middleware
– Architectures for robotics and automation systems
– Applications of embedded and cyber-physical systems
– High-performance and large scale parallel computing
– Approximate computing
– Post-Moore Architectures, including but not limited to quantum and neuromorphic computing

Submissions should be done through the link that is provided on the conference website. Papers must be submitted in PDF format. They should be formatted according to Springer LNCS style and must not exceed 12 pages, including references and figures.

The proceedings of ARCS 2017 will be published in the Springer Lecture Notes on Computer Science (LNCS) series. After the conference, it is planned that authors of selected papers will be invited to submit an extended version of their contribution for publication in a special issue of the Journal of Systems Architecture. Further, a best paper and best presentation award will be presented at the conference.

Proposals for workshops and tutorials within the technical scope of the conference are solicited. Submissions should be done through email directly to the corresponding chair: Carsten Trinitis (

General Co-Chairs:
Jens Knoop, Vienna University of Technology, Austria
Wolfgang Karl, Karlsruhe Institute of Technology, Germany

Program Co-Chairs:
Martin Schulz, Lawrence Livermore National Laboratory, USA
Koji Inoue, Kyushu University, Japan

Workshop and Tutorial Co-Chairs:
Carsten Trinitis, Technische Universität München, Germany

Publicity Chair:
Miquel Pericàs, Chalmers University of Technology, Sweden

Publication Chair:
Thilo Piontek, Magdeburg University, Germany