Call for Participation: Learning gem5 Tutorial

Learning gem5 Tutorial
in conjunction with HPCA 2017
http://learning.gem5.org/tutorial
Austin, USA
February 5, 2017

We will be holding a Learning gem5 Tutorial and a gem5 coding sprint at HPCA 2017 on February 5th in Austin, TX. The morning will consist of a “Learning gem5” half-day course. In the afternoon, we invite all gem5 developers senior, junior, and new developers to a “coding sprint.”

Morning: Learning gem5 tutorial is a half-day course on getting started with gem5. The goal is to leave the course with a solid foundation so you can be more productive using gem5 to explore your research aims. The main audience is first or second year computer architecture students who are interested in using gem5 for their graduate studies. Anyone who wants to learn basic gem5 best-practices are encouraged to attend.

Afternoon: During the gem5 coding sprint we will have a number of small projects that can be completed in an afternoon for developers to tackle. These are perfect opportunities to get started giving back to the gem5 community. We will pair senior developers with new contributors so you can get a feel for how the development community functions. Everyone is invited to participate.

Additional details can be found at the event web site.

Call for Paper: ICS 2017

International Conference on Supercomputing (ICS 2017)
http://press3.mcs.anl.gov/ics2017
Chicago, USA
June 14-16, 2017

IMPORTANT DATES (all deadlines are Anywhere on Earth)
Abstract submission: January 11, 2017
Paper submission: January 18, 2017
Author rebuttal period: March 5-7, 2017
Author notification: March 21, 2017
Camera-ready papers due: April 15, 2017

ICS is the premier international forum for the presentation of research results in high-performance computing. Papers are solicited on all aspects of research, development, and application of high-performance computing systems, including but not limited to the following:

– Computer architecture and hardware, including multicore, manycore and multiprocessor systems from small to very large scales, components in such systems such as accelerators, memory systems, storage architectures, interconnection networks at various levels, and heterogeneous systems

– Programming and execution models for high-performance computing, including new paradigms, languages, task creation and specification models, domain-specific language/programming support

– Static and dynamic compilation: optimization techniques to exploit all aspects of high performance architectures and auto-tuning techniques

– Runtime and system software support for high-performance computing, including task and resource management at chip-level, cluster-level, up to the level of large-scale academic/commercial computing service infrastructure, debugging, fault-tolerance, power/energy management, file systems, and performance evaluation/monitoring

– New computational algorithms and their applications for high performance computing systems

– Workload characterization empirical studies especially those on new scientific and commercial applications that pose significant challenges, and studies of highly experimental real systems

– Data intensive high performance computing: system support, algorithm design and application development for high performance computing that deal with large-scale collected data sets.

The review process will include a rebuttal period, and the papers will be judged based on novelty, technical soundness, and potential impact on the field.

SUBMISSION GUIDELINES:
Submissions should be a maximum of ten (10) pages, including references. Submissions (both abstract and paper) should be prepared for double blind review, i.e., without author names, or other identifying material in the submission. Authors should refer to themselves in the 3rd person when citing their own work. Further details available on the conference web site.

ORGANIZERS:
General Co-Chairs:
William Gropp, University of Illinois, Urbana-Champaign
Pete Beckman, Argonne National Laboratory / Northwestern University

Program Co-Chairs
Zhiyuan Li, Purdue University
Francisco J. Cazorla, Barcelona Supercomputing Center

Call for Papers: HPDC 2017

The 26th International ACM Symposium on High-Performance Parallel and Distributed Computing (HPDC)
http://hpdc.org/2017
Washington D.C., USA
June 26-30, 2017

IMPORTANT DATES:
Abstracts (required) due: January 10, 2017
Full Papers due: January 17, 2017 (no extensions)
Author notifications: March 29, 2017
Camera Ready: April 12, 2017

The ACM International Symposium on High-Performance Parallel and Distributed Computing (HPDC) is the premier annual conference for presenting the latest research on the design, implementation, evaluation, and the use of parallel and distributed systems for high-end computing.

Submissions are welcomed on high-performance parallel and distributed computing (HPDC) topics including but not limited to: clouds, clusters, grids, big data, massively multicore, and extreme-scale computing systems. Submissions that focus on the operating systems, runtime environments, architectures, and networks of high end computing systems are particularly encouraged. Experience reports of operational deployments that provide significantly novel insights for future research on HPDC applications and systems will also receive special consideration. All papers will be evaluated for their originality, technical depth and correctness, potential impact, relevance to the conference, and quality of presentation. Research papers must clearly demonstrate research contributions and novelty, while experience reports must clearly describe lessons learned and demonstrate impact.

In the context of high-performance parallel and distributed computing, the topics of interest include, but are not limited to:
– Operating systems, networks, and architectures
– High performance runtime environments
– Massively multicore systems, including heterogeneous systems
– Datacenter technology, resource virtualization
– Programming languages, APIs, and system interoperation approaches
– File and storage systems, I/O, and data management
– Big data stacks and big data ecosystems
– Resource management and scheduling, including energy-aware techniques
– Performance modeling, analysis, and engineering
– Fault tolerance, reliability, and availability
– Operational guarantees, and risk assessment and management
– Traditional and emerging applications and services that depend upon high-end computing

SUBMISSION GUIDELINES:
Authors are invited to submit technical papers of at most 12 pages in PDF format, including figures and references. Papers should be formatted in the ACM Proceedings Style and submitted via the conference web site. Accepted papers will appear in the conference proceedings, and will be incorporated into the ACM Digital Library. A limited number of papers will be accepted as posters.

Papers must be self-contained and provide the technical substance required for the program committee to evaluate their contributions. Submitted papers must be original work that has not appeared in and is not under consideration for another conference or a journal. See the ACM Prior Publication Policy for more details. Papers can be submitted at https://ssl.linklings.net/conferences/hpdc/.

ORGANIZERS:
General Co-Chairs:
Howie Huang, George Washington University, USA
Jon Weissman, University of Minnesota, USA

Program Co-Chairs:
Adriana Iamnitchi, University of South Florida, USA
Alexandru Iosup, TU Delft and Vrije Universiteit Amsterdam, the Netherlands

Program Committee:
Sameer Al-Kiswany, University of Waterloo, Canada
Gabriel Antoniu, INRIA, Rennes, France
Henri Bal, Vrije Universiteit Amsterdam, the Netherlands
Michela Becchi, University of Missouri, USA
Patrick Bridges, University of New Mexico, USA
Ali Butt, Virginia Tech, USA
Franck Cappello, Argonne National Laboratory, USA
Abhishek Chandra, University of Minnesota, USA
Andrew A. Chien, University of Chicago and Argonne National
Laboratory, USA
Frederic Desprez, INRIA, France
Peter Dinda, Northwestern University, USA
Dick Epema, Delft University of Technology, the Netherlands
Gilles Fedak, INRIA/ENS Lyon, France
Renato Figueiredo, University of Florida, USA
Liana Fong, IBM, USA
Haryadi Gunawi, University of Chicago, USA
Salim Hariri, University of Arizona, USA
David Irwin, University of Massachusetts at Amherst, USA
John (Jack) Lange, University of Pittsburgh, USA
Adrien Lebre, French Institute for Research in Computer Science, France
Jay Lofstead, Sandia National Laboratories, USA
Arthur Maccabe, Oak Ridge National Laboratory, USA
Satoshi Matsuoka, Tokyo Inst. Technology, Japan
Alberto Montresor, University of Trento, Italy
Christine Morin, INRIA, France
Radu Prodan, University of Innsbruck, Austria
Matei Ripeanu, University of British Columbia, Canada
Martin Schulz, Lawrence Livermore National Lab, USA
Yogesh Simmhan, Indian Institute of Science, India
Evgenia Smirni, College of William and Mary, USA
Shuaiwen Leon Song, Pacific Northwest National Lab, USA
Michela Taufer, University of Delaware, USA
Kenjiro Taura, The University of Tokyo, Japan
Douglas Thain, University of Notre Dame, USA
Ana Lucia Varbanescu, University of Amsterdam, the Netherlands
Rich Wolski, University of California at Santa Barbara, USA
Ming Zhao, Arizona State University, USA

Steering Committee:
Franck Cappello, Argonne National Lab, USA and INRIA, France
Peter Dinda, Northwestern University
Salim Hariri, University of Arizona
Dean Hildebrand, IBM Research Almaden
Jack Lange, University of Pittsburgh
Arthur Maccabe, Oak Ridge National Lab
Manish Parashar, Rutgers University
Kenjiro Taura, The University of Tokyo, Japan
Michela Taufer, University of Delaware
Douglas Thain, University of Notre Dame
Jon Weissman, University of Minnesota (Chair)
Dongyan Xu, Purdue University

Call for Papers: IEEE Symposium on Computer Arithmetic

24th IEEE Symposium on Computer Arithmetic (ARITH)
http://arith24.arithsymposium.org
July 24-26, 2017
London, UK

IMPORTANT DATES:
Paper submission deadline: Dec 31, 2016
Acceptance notification: Mar 31, 2017
Deadline for upload of final versions: Apr 30, 2017
Early registration deadline: Jun 1, 2017

Since 1969, the ARITH symposia have served as the flagship conference for presenting scientific work on the latest research in computer arithmetic. Authors are invited to submit papers describing recent advances on all aspects of computer arithmetic and its applications or implementations. This includes, but is not restricted to, the following topics:
– Arithmetic processor design and implementation
– Arithmetic algorithms and their analysis
– Floating-point units, algorithms, and numerical analysis
– Elementary and special function implementations
– Power-efficient or low-energy arithmetic units and processors
– Industrial implementation of arithmetic units and processors
– Test, validation, and formal verification techniques for arithmetic implementations
– Fault/error-tolerance in arithmetic implementations
– Arithmetic for FPGAs and reconfigurable logic
– Design automation for computer arithmetic implementations
– Computer arithmetic for security and cryptography
– Arithmetic to enhance accuracy or reliability (multiple-precision, interval arithmetic, …)
– Arithmetic challenges in HPC and exascale computing (accuracy, reproducibility, …)
– Arithmetic for specific application domains (big-data analytics, signal processing, computer graphics, multimedia, computer vision, finance, …)
– Computer arithmetic in emerging technologies
– Non-conventional computer arithmetic and applications

SUBMISSION GUIDELINES:
A PDF version of the full paper should be submitted no later than December 31st, 2016. Papers under review elsewhere are not acceptable for submission to ARITH. By submitting a paper you implicitly confirm you are solely submitting it to ARITH. Authors will be notified of acceptance in March 2017, and final camera-ready papers will be due in May 2017.

The final submissions of accepted papers cannot exceed 8 pages (NO extra pages) using the IEEE Computer Society Conference format (two columns). However, for review, authors may submit a paper with a maximum of 20 pages, 12pt font size, single column and double spacing.

Submission site: https://easychair.org/conferences/?conf=arith24

ORGANIZERS:
General Chairs:
Neil Burgess, ARM, UK

Program Chairs:
Javier Bruguera, ARM, USA
Florent de Dinechin, INSA Lyon, France

Call for Papers: JLPEA special issue on Emerging Network-on-Chip Architectures for Low Power Embedded Systems

Journal of Low Power Electronics and Applications (JLPEA)
Special issue on Emerging Network-on-Chip Architectures for Low Power Embedded Systems
http://www.mdpi.com/journal/jlpea/special_issues/embedded_systems

Deadline for manuscript submissions: January 31, 2017

Network-on-Chip emerged in recent years as a viable solution for the design of manycore embedded systems of the next generation. However, communication infrastructure scalability, memory bottleneck and parallelization of tasks, just to cite few examples, are becoming the limiting factors that hardware designers and software developers will be facing in the upcoming years.

This Special Issue on “Emerging Network-on-Chip Architectures for Low Power Embedded Systems” will focus on emerging approaches and recent advances on architectures, design techniques, modeling and prototyping solutions for the design of power/performance efficient Network-on-Chip systems in the manycore era.

Guest Editor: Prof. Dr. Davide Patti

Call for Papers: Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era

The 3rd IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era (HiPINEB 2017)
http://hipineb.i3a.info/hipineb2017
in conjunction with the HPCA 2017
Austin, Texas, USA
February 5, 2017

IMPORTANT DATES (All deadlines are 11:59 p.m. anywhere on Earth)
Paper submission due: 7 December, 2016
Notification of acceptance: 3 January, 2017
Early Registration due: 6 January, 2017
Camera-ready papers due: 10 January, 2017
Workshop date: 5 February, 2017

By the year 2023, High-Performance Computing (HPC) Systems are expected to break the performance barrier of the Exaflop (10^18 FLOPS) while their power consumption is kept at current levels (or increases marginally), what is known as the Exascale challenge. In addition, more storage capacity and data-access speed is demanded to HPC clusters and datacenters to manage and store huge amounts of data produced by software applications, what is known as the Big-Data challenge. Indeed, both the Exascale and Big-Data challenges are driving the technological revolution of this decade, motivating big research and development efforts from industry and academia. In this context, the interconnection network plays an essential role in the architecture of HPC systems and datacenters, as the number of processing or storage nodes to be interconnected in these systems is very likely to grow significantly to meet the higher computing and storage demands. Besides, the capacity of the network links is expected to grow, as the roadmaps of several interconnect standards forecast. Therefore, the interconnection network should provide a high communication bandwidth and low latency, otherwise the network becoming the bottleneck of the entire system. In that regard, many design aspects are considered when it comes to improving the interconnection network performance, such as topology, routing algorithm, power consumption, reliability and fault tolerance, congestion control, programming models, control software, etc.

The main goal of the third edition of HiPINEB is to gather and discuss in a full-day event the latest and most prominent efforts and advances, both from industry and academia, in the design and development of scalable high-performance interconnection networks, especially those oriented to meet the Exascale challenge and Big-data demands.

The list of topics covered by this workshop includes, but is not limited to, the following:
– Interconnect architectures and network technologies for high-speed, low-latency interconnects.
– Scalable network topologies, suitable for interconnecting a huge number of nodes.
– Power saving policies in the interconnect devices and network infrastructure, both at software and hardware level.
– Good practices in the configuration of the network control software.
– Network communication protocols: MPI, RDMA, MapReduce, etc.
– APIs and support for programming models.
– Routing algorithms.
– Quality of Service (QoS).
– Reliability and Fault tolerance.
– Load balancing and traffic scheduling.
– Network Virtualization.
– Congestion Management.
– Applications and Traffic characterization.
– Modeling and simulation tools.
– Performance Evaluation.
– Interfacing accelerators through the interconnect (GPUs, Xeon Phi, etc).
– Network infrastructure in distributed storage, distributed databases and Big-Data.

Furthermore, short papers in the above topics will be also taken into consideration, as long as they are based on emerging ideas, work-in-progress and early, high-impact achievements.

Note, however, that papers focused on topics that are too far from the design, development and configuration of high-performance interconnects for HPC systems and Datacenters (e.g., mobile networks, intrusion detection, peer-to-peer networks or grid/cloud computing) will be automatically considered as out of scope and rejected without review.

SUBMISSION GUIDELINES:
Regular and short papers must be in PDF format and should include title, authors and affiliations as well as the e-mail address of the contact author. Submitted regular manuscripts may not exceed 8 single-spaced double-column pages using 10-point size font on 8.5×11 inch pages, including figures, tables, and references. Short papers may not exceed 4 single-spaced double-column pages using 10-point size font on 8.5×11 inch pages. At least one author of the paper must be registered for the conference workshop.

HiPINEB manuscript submissions are managed by easyChair. To submit a paper, go to https://easychair.org/conferences/?conf=hipineb2017 and follow the instructions.

REVIEW PROCESS:
Authors are entitled to submit original papers of high technical quality, according to the list of topics described above. Papers will be reviewed based on originality, novelty, technical strength, presentation quality, correctness and relevance to the conference scope.

WORKSHOP PROCEEDINGS:
Papers will be published in the HiPINEB proceedings, edited by the IEEE CPS which will be submitted for indexing and inclusion in IEEE Xplore and CSDL.

SPECIAL ISSUE:
Best papers among those selected for HiPINEB 2017 will be published in the Special Issue on “Trends in High-Performance Interconnection Networks in the Exascale and Big-Data Era 2017”, to be published in the Journal of Concurrency and Computation: Practice and Experience, Wiley, (2015 Impact Factor: 0.942). Further details in http://hipineb.i3a.info/hipineb2017/special-issue

PROGRAM HIGHLIGHTS:
– Keynote: Bill Dally, NVIDIA
– Technical sessions: Presentation of regular and short papers
– Panel: TBA

ORGANIZERS:
– Pedro Javier Garcia, University of Castilla-La Mancha, Spain
– Jesus Escudero-Sahuquillo, University of Castilla-La Mancha, Spain

Program Committee:
– Francisco J. Alfaro, University of Castilla-La Mancha, Spain
– Jose Cano-Reyes, University of Edinburgh, United Kingdom
– Lizhong Chen, Oregon State University, USA
– Nikolaos Chrysos, FORTH, Greece
– Holger Fröning, University of Heidelberg, Germany
– Maria Engracia Gomez, Technical University of Valencia, Spain
– Ernst Gunnar Gran, Simula Research Laboratory, Norway
– Ryan E. Grant, Sandia National Laboratories, USA
– Mitch Gusat, IBM Research, Switzerland
– Scott Hemmert, Sandia National Laboratories, USA
– John Kim, KAIST, South Korea
– Michihiro Koibuchi, National Institute of Informatics, Japan
– Yuho Jin, New Mexico State University, USA
– Pedro Lopez, Technical University of Valencia, Spain
– Jose Miguel Montañana, University of York, United Kingdom
– Gaspar Mora, Intel Corporation, USA
– Mondrian Nuessle, Extoll, Germany
– Julio Ortega, University of Granada, Spain
– Thibaut Palfer-Sollier, Numascale AS, Norway
– Dhabaleswar K. Panda, The Ohio State University, USA
– Matthieu Perotin, ATOS BULL, France
– Mikel Eukeni Pozo Astigarraga, CERN, Switzerland
– Samuel Rodrigo, Oracle Corporation, Norway
– Sebastien Rumley, Columbia University, USA
– Jose Luis Sanchez, University of Castilla-La Mancha, Spain
– Heiko Joerg Schick, Huawei Technologies, Germany
– Jörn Schumacher, CERN, Switzerland
– Alex Shpiner, Mellanox Technologies, Israel
– Evangelos Tasoulas, Simula Research Laboratory, Norway
– Francisco Triviño, Oracle Corporation, Norway
– Luis Tomas, Red Hat, Spain
– Enrique Vallejo, University of Cantabria, Spain
– Wainer Vandelli, CERN, Switzerland
– Pierre Vigneras, ATOS BULL, France

Call for Papers: PACT 2017

26th International Conference on Parallel Architectures & Compilation Techniques (PACT)
http://pactconf.org
Portland, Oregon, USA
September 9-13, 2017

IMPORTANT DATES:
Paper Deadline: March 14, 2017
Author Response Period: May 3-6, 2017
Author Notification: May 24, 2017
Camera Ready Final Papers: July 19, 2017

The purpose of PACT 2017 is to bring together researchers from architecture, compilers, applications and languages to present and discuss innovative research of common interest.

PACT started as a Data Flow Workshop in conjunction with ISCA 1989 but quickly evolved into a unique venue at the intersection of classical parallel architecture and compilers.

Recently, PACT widened its scope to include insights useful for the design of machines and compilers from applications such as, but not limited to, machine learning, data analytics and computational biology.

PACT solicits novel papers, workshops, tutorials, and entries to an ACM student research competition on a broad range of topics that include, but are not limited to:
– Parallel architectures and computational models
– Compilers and tools for parallel computer systems
– Multicore, multithreaded, superscalar, and VLIW architectures
– Compiler/hardware support for hiding memory latencies
– Support for correctness in hardware and software
– Reconfigurable parallel computing
– Dynamic translation and optimization
– I/O issues in parallel computing and their relation to applications
– Parallel programming languages, algorithms and applications
– Middleware and run time system support for parallel computing
– Application-specific parallel systems
– Applications and experimental systems studies of parallel processing
– Relevant aspects of distributed computing and mobile computing
– Heterogeneous systems using various types of accelerators
– Insights from modern parallel applications (e.g., machine learning, data analytics, and computational biology) for the design of parallel architectures and compilers.

SUBMISSION GUIDELINES:
Submitted papers will be evaluated on technical merits and clarity of presentation. Papers must contain sufficient information and be organized in such a way that their technical contribution and significance can be understood by a wide audience of computer scientists.

Submitted papers must be original material that has not been previously published in another conference or journal, nor is currently under review by another conference or journal. Papers are to be submitted for double-blind review. This means that author names as well as hints of identity are to be removed from the submitted paper.

Authors of accepted papers will be invited to formally submit their supporting materials to the Artifact Evaluation Committee. The task of this committee is to assess how the artifacts support the work described in the papers. Submission is volunta ry. Papers that go through the artifact evaluation process successfully will receive a seal of approval which will be printed on the first page of the papers in the proceedings.

ORGANIZERS:
General Chair: Ravi Iyer, Intel
Program Chair: David Padua, University of Illinois

Call for Workshops and Tutorials: ISCA 2017

The 44st Annual International Symposium on Computer Architecture (ISCA)
http://isca17.ece.utoronto.ca/
Toronto, Ontario, Canada
June 24-25, 2017 Workshops and Tutorials
June 26-28, 2017 Main Conference

CALL FOR WORKSHOPS

Please send workshop proposals to Juan Luis Aragón at jlaragon@ditec.um.es by Thursday December 15, 2016. Proposers will be notified of workshop decisions by Friday January 20, 2017.

All workshop proposals should include the following information:
– Title of the workshop
– Organizers and their affiliations
– Description of main objectives
– Sample call for papers, including the workshop’s main topics
– Expected duration of the workshop; i.e., 1/2 day, full day, or 2 days
– If the workshop has been held before, the location (i.e., which conference), date, the number of published papers and attendees at the last occurrence

CALL FOR TUTORIALS

Please send tutorial proposals to Paul V. Gratz at ISCA44_Tutorials@gratz1.com> by Thursday, December 15, 2016. Proposers will be notified of tutorial decisions by Friday January 20, 2017.

All tutorial proposals should include the following information:
– Title of the tutorial
– List of organizers and presenters, including their affiliations and short bios
– Abstract of the tutorial, including main objectives
– A list of topics to be covered, including format (e.g., talks, demos, etc), target audience, and prerequisite knowledge
– Expected duration of the tutorial (i.e., 1/2 day, full day, or 2 days)
– If the tutorial has been held before, the location (i.e., which conference), date, the number of published papers and attendees at the last occurrence

Call for Papers: Non-Volatile Memory Workshop 2017

Non-Volatile Memory Workshop 2017
http://nvmw.ucsd.edu
University of California, San Diego, USA
March 12-14, 2017

IMPORTANT DATES:
The submission deadline: December 2, 2016
Notification of acceptance: January 23, 2017

The 8th Annual Non-Volatile Memories Workshop (NVMW 2017) provides a unique showcase for outstanding research on solid state, non-volatile memories. It features a “vertically integrated” program that includes presentations on devices, data encoding, systems architecture, and applications related to these exciting new data storage technologies. Last year’s workshop (NVMW 2016) included 40 speakers from top universities, industrial research labs, and device manufacturers and attracted nearly 230 attendees. (The website for NVMW 2016 can be found at http://nvmw.ucsd.edu/2016.) NVMW 2017 will build on this success.

The organizing committee is soliciting presentations on any topic related to non-volatile, solid state memories, including:
– Advances in memory devices or memory cell design.
– Characterization of commercial or experimental memory devices.
– Error correction and data encoding schemes for non-volatile memories.
– Advances in non-volatile memory-based storage systems.
– Operating system and file system designs for non-volatile memories.
– Security and reliability of solid-state storage systems.
– Applications of non-volatile memories to scientific, “big data”, and high-performance workloads.
– Implications of non-volatile memories for applications such as databases and NoSQL systems.

The goal is to facilitate the exchange of the latest ideas, insights, and knowledge that can propel future progress. To that end, presentations may include new results or work that has already been published during the 18 months prior to the submission deadline. In lieu of printed proceedings, we will post the slides and extended abstracts of the presentations online. Presentation of new work at the workshop does not preclude future publication.

SUBMISSION GUIDELINES:
Workshop submissions should be in the form of a 2-page presentation abstract. Submissions will be evaluated on the basis of impact, novelty, and general interest.

Further details on abstract submission, technical program, tutorials, travel, social program, and travel grant will be provided on this website.

ORGANIZERS:
Paul Siegel, UCSD ECE/CMRR
Eitan Yaakobi, Technion
Steven Swanson, UCSD CSE
Hung-wei Tseng, NC State University

Call for Papers: IEEE Transactions on Multi-Scale Computing Systems, Special Issue on Emerging Technologies and Architectures for Manycore Computing

IEEE Transactions on Multi-Scale Computing Systems
Special Issue on Emerging Technologies and Architectures for Manycore Computing

https://www.computer.org/web/tmscs

IMPORTANT DATES:
Open for submissions in ScholarOne Manuscripts: October 1, 2016
Closed for submissions: December 1, 2016
Results of first round of reviews: March 1, 2017
Submission of revised manuscripts: April 1, 2017
Results of second round of reviews: May 1, 2017
Publication materials due: June 1, 2017

The pursuit of Moore’s Law is slowing and the exploration of alternative devices is underway to replace the CMOS transistor and traditional architectures at the heart of data processing. Moreover, the emergence of stringent application constraints, particularly those linked to energy consumption, require new system architectural strategies (e.g. manycore) and real-time operational adaptability approaches. Such complex systems require new and powerful design and programming methods to ensure optimal and reliable operation. This special issue aims at collating new research along all the dimensions of emerging technologies and architectures for computing in manycores.

The topics of interest include, but are not limited to:
– Emerging on-chip computing technologies and architectures
– Many-core architecture customization, heterogeneous architectures
– Runtime resource management (energy, memory, reliability …)
– Programming models, languages, compilers and virtualization techniques for new computing paradigms

SUBMISSION GUIDELINES:
Prospective authors are invited to submit their manuscripts electronically after the “open for submissions” date, adhering to the /IEEE Transactions on Multi-Scale Computing Systems/ guidelines (http://www.computer.org/portal/web/tmscs/author). Please submit your papers through the online system (https://mc.manuscriptcentral.com/tmscs-cs) and be sure to select the special issue name. /Manuscripts should not be published or currently submitted for publication elsewhere/. Please submit only full papers intended for review, not abstracts, to the ScholarOne portal.

GUEST EDITORS:
Sébastien Le Beux, Ecole Centrale de Lyon (France)
Paul V. Gratz, Texas A&M University (USA)
Ian O’Connor, Ecole Centrale de Lyon (France)