Call for Papers: NoCArc 2016

9th International Workshop on Network on Chip Architectures
in conjunction with IEEE/ACM MICRO-49
October 15 or 16, 2016
Taipei, Taiwan

IMPORTANT DATES
– Abstract submission deadline: July 25, 2016
– Paper submission deadline: August 1, 2016
– Acceptance notification: September 1, 2016
– Camera-ready version due: September 8, 2016

Current multicore architectures formed by tens of processing cores will be soon replaced by the next generation of manycore architectures with hundreds of cores. In fact, the International Technology Roadmap for Semiconductors foresees that the number of Processing Elements (PEs) that will be integrated into a System-on-Chip (SoC) will be in the order of thousand within the 2020. As the number of communicating elements increases, there is a need for an efficient, scalable and reliable communication infrastructure. As technology geometries shrink to the deep submicron regime, however, the communication delay and power consumption of global interconnections become the major bottleneck. The Network-on- Chip (NoC) design paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues such as performance limitations of long interconnects, and integration of large number of PEs on a chip.

The goal of NoCArc workshop is to provide a forum for researchers to present and discuss innovative ideas and solutions related to design and implementation of multi-core systems on chip. The workshop will focus on issues related to design, analysis and testing of on-chip networks.

The workshop will focus on issues related to design, analysis and testing of on-chip networks. The topics of specific interest for the workshop include, but are not limited to:

NoC Architecture and Implementation
– Topologies, routing, flow control
– Managing QoS
– Timing, synchronous/asynchronous communication
– Reliability issues
– Design methodologies and tools
– Signaling & circuit design for NoC links
– NoC Analysis and Verification

Power, energy and thermal issues
– Benchmarking and experience with NoC-based systems
– Modeling, simulation, and synthesis
– Verification, debug and test
– Metrics and benchmarks
– NoC Application

Mapping of applications onto NoCs
– NoC case studies, application-specific NoC design
– NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
– NoC designs for heterogeneous systems
– On-Chip Communication Optimization

Communication efficient algorithms
– Multi/many-core communication workload characterization and evaluation
– Energy efficient NoCs and energy minimization
– NoC at System-level

Design of memory subsystem
– NoC support for memory and cache access
– OS support for NoCs
– Programming models including shared memory, message passing and novel programming models
– Issues related to large-scale systems (datacenters, supercomputers) with NoC-based systems as building blocks

Emerging NoC Technologies
– Wireless, Optical, and RF
– NoCs for 3D and 2.5D packages

Besides regular papers, papers describing work in progress or incomplete but sound new innovative ideas related to the workshop theme are also encouraged.

SUBMISSION GUIDELINES:
Both research and application-oriented papers are welcome. All papers should be submitted electronically by EasyChair. Papers must be in PDF format and should include title, authors and affiliation, e-mail address of the contact author. Additional information at http://www.unikore.it/nocarc/submission.html

ORGANIZERS:
General Co-Chairs
– Maurizio Palesi, Univ. of Enna, KORE, Italy
– Masoud Daneshtalab, Univ. of Turku, Finland and KTH, Sweden
– Xiaohang Wang, South China University of Technology, China

TPC Co-Chairs
– Masoumeh Ebrahimi, Univ. of Turku, Finland
– Davide Patti, Univ. of Catania, Italy

Call for Nominations: Seymour Cray, Sidney Fernbach & ACM/IEEE-CS Ken Kennedy Awards

Call for Nominations: Seymour Cray, Sidney Fernbach & ACM/IEEE-CS Ken Kennedy Awards
Award Presentation: SC16
Salt Lake City, Utah, USA
Nov 14-18, 2016

Nomination Deadline: July 1, 2016

SEYMOUR CRAY COMPUTER ENGINEERING AWARD
Established in late 1997 in memory of Seymour Cray, the Seymour Cray Award is awarded to recognize innovative contributions to high performance computing systems best exemplify the creative spirit demonstrated by Seymour Cray. The award consists of a crystal memento and honorarium of $10,000. This award requires 3 endorsements.

SIDNEY FERNBACH MEMORIAL AWARD
Established in 1992 by the Board of Governors of the IEEE Computer Society. It honors the memory of the late Dr. Sidney Fernbach, one of the pioneers on the development and application of high performance computers for the solution of large computational problems. The award, which consists of a certificate and a $2,000 honorarium, is presented annually to an individual for “an outstanding contribution in the application of high performance computers using innovative approaches.” This award requires 3 endorsements.

ACM/IEEE-CS KEN KENNEDY AWARD
Established in memory of Ken Kennedy, the founder of Rice University’s nationally ranked computer science program and one of the world’s foremost experts on high-performance computing. A certificate and $5,000 honorarium are awarded jointly by the ACM and the IEEE Computer Society for outstanding contributions to programmability or productivity in high- performance computing together with significant community service or mentoring contributions. This award requires 2 endorsements.

For nomination queries, please write to awards@computer.org or visit http://www.computer.org/portal/web/awards/faq

Call for Papers: HPCA 2017

23rd IEEE International Symposium on High-Performance Computer Architecture (HPCA)
collocated with CGO and PPoPP
Austin, Texas, USA
February 4 – 8, 2017

IMPORTANT DATES:
Abstract submission: July 25, 2016, 11:59 PM CDT
Paper submission: August 1, 2016, 11:59 PM CDT
Notification of paper outcome: October 12, 2016

The International Symposium on High-Performance Computer Architecture provides a high-quality forum for scientists and engineers to present their latest research findings in this rapidly-changing field. Authors are invited to submit papers on all aspects of high-performance computer architecture.

Topics of interest include, but are not limited to:
– Processor, cache, and memory architectures
– Parallel computer architectures
– Multicore and multiprocessor architectures
– Impact of technology on architecture
– Power-efficient architectures and techniques
– Dependable/secure architectures
– High-performance I/O systems
– Embedded, reconfigurable, and heterogeneous architectures
– Interconnect and network interface architectures
– Architectures for cloud-based HPC and data centers
– Innovative hardware/software trade-offs
– Impact of compilers and system software on architecture
– Performance modeling and evaluation
– Architectures for emerging technology and applications

Authors should submit an abstract by July 25, 2016 11:59 PM CDT. They should submit the full version of the paper August   1, 2016, 11:59 PM CDT. No extensions will be granted. The full version should be a PDF file following the submission guidelines that will be made available at the submission website.  Papers should be submitted for blind review. We anticipate making a Best Paper award; all papers will be evaluated based on their novelty, fundamental insights, experimental evaluation, and potential for long-term impact.  New-idea papers as well as papers that significantly advance established areas are strongly encouraged. Submission issues should be directed to the program chair at djimenez@cse.tamu. edu . Details formatting and submission guidelines will be made available at http://hpca23.cse.tamu.edu. HPCA-23 will host an Industrial Paper Session presenting novel insights from industry. See the HPCA 2017 website for submission details.

Sponsored by the IEEE Computer Society TC on Computer Architecture

ORGANIZERS:
General Chair:
Derek Chiou, Microsoft and UT Austin

Program Chair:
Daniel A. Jimenez, Texas A&M University

Program Committee:
Valeria Bertacco, Michigan
Abhishek Bhattacharjee, Rutgers
Reetuparna Das, Michigan
Hadi Esmaeilzadeh, Georgia Tech
Yoav Etsion, Technion
Babak Falsafi, EPFL
Michael Ferdman, Stony Brook University
Antonio Gonzalez, UPC
Paul Gratz, Texas A&M
Nikos Hardavellas, Northwestern University
Kei Hiraki, University of Tokyo
Jaehyuk Huh, KAIST
Engin Ipek, Rochester
David Kaeli, Northeastern
Samira Khan, UVA
Hyesoon Kim, Georgia Tech
Tao Li, Florida and NSF
Calvin Lin, UT Austin
Gabriel H. Loh, AMD
Shih-Lien Lu, TSMC
Pierre Michaud, Inria
Timothy N. Miller, Binghamton University (SUNY)
Miquel Moreto, BSC and UPC
Andreas Moshovos, Toronto
Trevor Mudge, Michigan
Onur Mutlu, ETH Zurich and CMU
Abdullah Muzahid, UT San Antonio
Vijay Nagarajan, University of Edinburgh
Soner Onder, Michigan Tech
Yale N. Patt, UT Austin
Miquel Pericas, Chalmers University of Technology
Alex Ramirez, NVIDIA
Karu Sankaralingam, Wisconsin
Yan Solihin, NCSU and NSF
Yingying Tian, AMD
Mohit Tiwari, UT Austin
Josep Torrellas, UIUC
Thomas F. Wenisch, Michigan
David Wentzlaff, Princeton
Carole-Jean Wu, ASU
Yuan Xie, UCSB
Mohamed Zahran, NYU
Antonia Zhai, Minnesota
Lixin Zhang, Institute of Computing Technology, CAS
Huiyang Zhou, NCSU

Industrial Session Chair:
Chris Wilkerson, Intel Labs

Local Arrangements Chair:
Mohit Tiwari, UT Austin

Workshops and Tutorials Chair:
Mike Ferdman, Stony Brook University

Finance Chair:
Dam Sunwoo, ARM

Publications Chair:
Xuehai Qian, USC

Travel Awards Chair:
Zhenman Fang, UCLA

Publicity Chair:
Michael Papamichael, Microsoft Research

Web and Submissions Chairs:
Hung-Wei Tseng, UCSD and Elvira Teran, Texas A&M and Intel Labs

Industrial Session Chair:
Chris Wilkerson, Intel Labs

Local Arrangements Chair:
Mohit Tiwari, UT Austin

Workshops and Tutorials Chair:
Mike Ferdman, Stony Brook University

Finance Chair:
Dam Sunwoo, ARM

Publications Chair:
Xuehai Qian, USC

Travel Awards Chair:
Zhenman Fang, UCLA

Publicity Chair:
Michael Papamichael, Microsoft Research

Web and Submissions Chairs:
Hung-Wei Tseng, UCSD and Elvira Teran, Texas A&M and Intel Labs

Call for Papers: CGO 2017

2017 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)
co-located with CC, HPCA and PPoPP
Austin, TX USA
February 4-8, 2017

IMPORTANT DATES
Abstract Submission: Sept 2, 2016
Paper Submission: Sept 9, 2016
Notification: Oct 25, 2016

The International Symposium on Code Generation and Optimization (CGO) provides a premier venue to bring together researchers and  practitioners working at the interface of hardware and software on a wide range of optimization and code generation techniques and related issues. The conference spans the spectrum from purely static to fully dynamic approaches, and from pure software-based methods to specific architectural features and support for code generation and optimization.

Original contributions are solicited on, but not limited to, the following topics:
– Code Generation, Translation, Transformation, and Optimization for performance, energy, virtualization, portability, security, or reliability concerns, and architectural support
– Efficient execution of dynamically typed and higher-level languages
– Optimization and code generation for emerging programming models, platforms, domain-specific languages
– Dynamic/static, profile-guided, feedback-directed, and machine learning based optimization
– Static, Dynamic, and Hybrid Analysis
– Program characterization methods
– Efficient profiling and instrumentation techniques; architectural support
– Novel and efficient tools
– Compiler design, practice and experience
– Compiler abstraction and intermediate representations
– Vertical integration of language features, representations, optimizations, and runtime support for parallelism
– Solutions that involve cross-layer (HW/OS/VM/SW) design and integration
– Deployed dynamic/static compiler and runtime systems for general purpose, embedded system and Cloud/HPC platforms
– Parallelism, heterogeneity, and reconfigurable architectures
– Optimizations for heterogeneous or specialized targets, GPUs, SoCs, CGRA
– Compiler-support for vectorization, thread extraction, task scheduling, speculation, transaction, memory management, data distribution and synchronization

ORGANIZERS
General Chair
Vijay Janapa Reddi, UT Austin

Program Co-chairs
Aaron Smith, Microsoft Research/University of Edinburgh
Lingjia Tang, University of Michigan

Program Committee
Adrian Sampson, Cornell
Albert Cohen, Inria
Alexandra Jimborean, UPPSALA
Antoniu Pop, University of Manchester
Ayal Zaks, Intel
Carol Eidt, Microsoft
Changhee Jung, Virginia Tech
Chenggang Wu, ICT
Christophe Dubach, University of Edinburgh
Derek Bruening, Google
Erik Altman, IBM
Evelyn Duesterwald, IBM
Jack Davidson, University of Virginia
Jason Mars, University of Michigan
Jennifer Sartor, UGhent
Jingling Xue, UNSW
Joe Devietti, University of Pennsylvania
Lisa Wu, UC Berkeley
Louis-Noel Pouchet, Ohio State University
Michael Carbin, MIT
Michael Laurenzano, University of Michigan
Michael O’Boyle, University of Edinburgh
Milind Chabbi, HP
Naveen Kumar, Google
Nuno Lopes, MSR Cambridge
Peng Wu, Huawei
Robert Hundt, Google
Saman Amarasinghe, MIT
Santosh Nagarakatte, Rutgers
Scott Mahlke, University of Michigan
Simone Campanoni, Northwestern University
Vinod Grover, Nvidia
Youfeng Wu, Intel
Yun Liang, Peking University

Finance Chair
Carol Eidt, Microsoft

Local Arrangements Chair
Mauricio Breternitz, AMD

Regional Publicity Chairs
Jason Mars, University of Michigan (North America)
Wei-Chung Hsu, NTU (Asia)
Simone Campanoni, Northwestern (Europe)
Edson Borin, Unicamp (South America)

Proceedings Chair
Antonia Zhai, University of Minnesota

Registration Chair
Carole Wu, Arizona State University

Sponsorship Chair
Robert Hundt, Google

Students/Travel Chair
Brandon Lucia, CMU

Web Chair
Matthew Halpern, UT Austin

Workshops/Tutorials Chair
Adrian Sampson, Microsoft Research/Cornell

Artifacts Chairs
Joseph Devietti, University of Pennsylvania
Grigori Fursin, Dividiti/cTuning Foundation

Call for contributions: FPL PhD Forum and Demo Night

Submitted by Mirjana Stojilovic
http://www.fpl2016.org

26th International Conference on Field-Programmable Logic and Applications (FPL)
Aug 29 – Sep 2, 2016
Lausanne, Switzerland
 

IMPORTANT DATES:
PhD Forum and Demo Night proposals deadline: May 8, 2016
Notifications: June 15, 2016
 

CALL FOR CONTRIBUTIONS TO PhD FORUM

FPL 2016 PhD Forum is tailored for PhD students in two ways: Firstly,
it is an excellent occasion for PhDs to present their work in progress
or preliminary results, and receive early feedback from other
researchers in the domain. Secondly, it is a unique opportunity for
PhD students who are finishing their studies to give a broad overview
of their work and draw attention to it from both the academic and
industrial worlds.

PhD Forum authors are invited to submit 2-page papers using the format
of FPL 2016 regular papers. PhD Forum papers should include clear
descriptions of thesis motivation, objectives, problem definition,
addressed solutions, current status, and planned work. Contributions
based on preliminary results or on work in progress are particularly
encouraged. Accepted PhD Forum papers will be included in the
conference proceedings and presented at a special poster session.
Prior to this session, presenters will be offered the opportunity to
draw attention to their posters through a short “elevator pitch”
(2-minute presentation).
 

CALL FOR CONTRIBUTIONS TO DEMO NIGHT

FPL 2016 Demo Night event is an excellent opportunity for conference
participants to demonstrate and disseminate their work, to increase
their visibility, and interact with attendees. Demonstrations may
include commercial and academic research-oriented tools, platforms,
systems, and more. The event will take place on one of the conference
evenings. Hors d’oeuvres and drinks will be offered to all attendees.

Demo Night presenters are invited to submit 1-page abstracts using the
same format as FPL 2016 regular papers. A cover page should be added
to the submission and should contain the following information:
– Demo title.
– Names and affiliations of all authors.
– Description of the main objectives and relevance of the demo to the
FPL community.
– Short biographies of demo presenters.
– Any logistical requirements the demonstration may have.

The 1-page abstract should include demo title, names and affiliations
of all authors, and an abstract of the demo. The authors of the
accepted demos will be asked to prepare a poster for the Demo Night.
All demo posters will be published on the FPL 2016 web page and the
abstracts will be included in the conference proceedings.
 

ORGANIZERS
FPL PhD Forum and Demo Night chairs:
Mirjana Stojilović, University of Applied Sciences Western Switzerland
Yann Thoma, University of Applied Sciences Western Switzerland

Call for Participation: ISPASS 2016

Submitted by Erik Hagersten
http://www.ispass.org/ispass2016
April 17 to April 19, 2016

Submitted by Erik Hagersten
http://www.ispass.org/ispass2016

The 17th International Symposium on Performance Analysis of
Systems and Software (ISPASS)

Uppsala, Sweden

April 17: Workshops/Tutorials (3 workshops and 4 tutorial)
April 18-19: Conference (including 3 keynotes)

Early registration: March 18
Hotel reservation: March 18

The name says it all: IEEE International Symposium on Performance Analysis of
Systems and Software. The focus is on performance-related problems, solutions,
methods and tools for software and system performance and power analysis
and optimisation.

After 16 years in the US, the ISPASS conference is now moving “abroad” for
the first time.

General Chair: Erik Hagersten, Uppsala University
Program Chair: Andreas Moshovos, University of Toronto

Call for Nominations: 2016 IEEE TCCA Young Computer Architect Award

Submitted by Kunle Olukotun

Submitted by Kunle Olukotun

The 2016 IEEE TCCA Young Computer Architect Award

Nomination deadline: April 15, 2016
 

The IEEE TCCA Young Computer Architect Award recognizes outstanding research
contributions by an individual in the field of Computer Architecture, who
received his/her PhD degree within the last 6 years. The Award will be
presented at the Awards Banquet at the 2016 International Symposium on
Computer Architecture (ISCA). The IEEE Computer Society administers the award.

Eligibility: The award is open to any individual who has completed his/her PhD
degree after April 15, 2010 (within last 6 years). At the discretion of the
awards committee, eligibility may be adjusted for documented family-related or
medical leaves from employment. The winner of the award will be someone who
has made an outstanding, innovative research contribution or contributions to
the field of Computer Architecture.

NOMINATION PROCESS:
Anyone can nominate a candidate (but no self-nominations). The following
information must be provided at the time of nomination:

1. Name/email of person making the nomination.

2. Name/email of candidate for whom the award is recommended.

3. A statement by the nominator (maximum of 500 words long) as to why
the nominee deserves the award. As the award is for outstanding contributions
in research, the statement and supporting letters should address the
contributions and why they are both outstanding and significant.

4. CV of the candidate.

5. The names and email addresses of two persons who the nominator has
contacted to supply supporting letters.

All materials, including the two supporting letters, should be sent to the Chair
of the Selection Committee by April 15, 2016. The award will be presented at
the Awards Banquet of the 43rd International Symposium on Computer
Architecture (ISCA) in Seoul, Korea, June 18-22, 2016.

SELECTION COMMITTEE:
Lieven Eeckhout (Ghent University)
Onur Mutlu (Carnegie Mellon University)
Kunle Olukotun (Stanford University) – Chair (kunle@stanford.edu)

PAST WINNERS:
2015: Prof. Ronald Dreslinski, The University of Michigan, in recognition of
outstanding research contributions in computer architectures for emerging
low-power circuit techniques

2014: Prof. Engin Ipek, The University of Rochester, in recognition of
outstanding research contributions for computer architectures that leverage
emerging technologies

2013: Prof. Luis Ceze, The University of Washington, in recognition of
outstanding research contributions for improving multi-core programmability
and correctness

2012: Prof. Karthikeyan Sankaralingam, The University of Wisconsin, in
recognition of outstanding contributions in the field of computer architecture
in both research and education

2011: Prof. Onur Mutlu, Carnegie Mellon University, in recognition of
outstanding contributions in the field of computer architecture in both
research and education

Available Now: IEEE Micro Special Issue on Near-Data Processing

Submitted by Lieven Eeckhout
http://online.qmags.com/MIC0116?sessionID=6D82D319BF01A05D0C8C0796A&cid=3196036&eid=19756#pg1&mode2

Submitted by Lieven Eeckhout
http://online.qmags.com/MIC0116?sessionID=6D82D319BF01A05D0C8C0796A&cid=3196036&eid=19756#pg1&mode2
IEEE Micro Special Issue on Near-Data Processing

The Jan/Feb 2016 IEEE Micro Special Issue on Near-Data Processing,
guest edited by Rajeev Balasubramonian (University of Utah) and Boris Grot
(University of Edinburgh), is now available. The issue includes expert opinions
and position statements on near-data processing along with in-depth articles.
The issue also features two testimonials on MICRO Test-of-Time Awards.

Call for Nominations: ACM SIGARCH Distinguished Service Award

Submitted by Natalie Enright Jerger
http://www.sigarch.org/awards/acm-sigarch-distinguished-service-award/

Submitted by Natalie Enright Jerger
http://www.sigarch.org/awards/acm-sigarch-distinguished-service-award/

ACM SIGARCH Distinguished Service Award

Nomination Deadline: April 8, 2016
 

This annual award is presented to an individual who has contributed important service to the computer architecture community.

Recipients receive a memento engraved with their name along with a $1000 honorarium. The award is presented by the SIGARCH chair at ISCA during ISCA’s award presentation session. The award recipient also receives up to $2000 towards support for travel costs, including airfare, hotel, and conference registration for ISCA. The recipient is listed with a citation for their award on the SIGARCH Distinguished Service Award web page. The list of past award
recipients is at http://www.sigarch.org/awards/acm-sigarch-distinguished-award-past-winners/

The selection committee consists of 3 or more members and is appointed by the
SIGARCH chair. The committee typically includes recent recipients of the award
and current SIGARCH executive committee members. The committee solicits
nominations from the computer architecture community in a variety of ways
including announcements in SIGARCH’s newsletter and postings on appropriate
newsgroups and websites. The committee considers all external nominations, plus
any internal nominations from members of the committee, in the context of the
nominees’ specific and general service contributions to the computer
architecture community.

NOMINATION PROCESS:

Nominations can be submitted at any time to the committee chair (Norm Jouppi,
jouppi@acm.org). Nominations submitted by April 8th will be considered for this
year’s award. A nomination for the distinguished service award that is not
awarded will remain valid for 3 years.

Each nomination should consist of the following items:
– Name, address, phone number, and email address of the person making the
nomination (the nominator).
– Name, address, phone number, and email address of the candidate for whom
an award is recommended (the nominee).
– A short statement (200-500 words) explaining why the nominee deserves the
award in question.
– Names and email addresses of 4-7 people who the nominator believes will
support the nomination.
– The awards committee will ask some of these people for their opinions.

Self-nominations are not allowed.

The 2016 selection committee is:
– Norman P. Jouppi (chair), Google, jouppi@acm.org
– Trevor Mudge,
 University of Michigan, 
tnm@eecs.umich.edu
– David Brooks,
 Harvard University, dbrooks@eecs.harvard.edu

Call for Papers: NVMSA 2016

Submitted by Onur Mutlu
https://sites.google.com/a/camelab.org/nvmsa-2016/
April 1, 2016

Submitted by Onur Mutlu
https://sites.google.com/a/camelab.org/nvmsa-2016/

The 4th IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA)
Daegu, Korea
August 17-19, 2016
 

IMPORTANT DATES:
April 1: Abstract Submission Deadline
April 14: Paper Submission Deadline
June 1: Acceptance notification
June 12: Camera ready
 

Non-Volatile memory (NVM) technologies have demonstrated great potential to
improve many aspects of present and future memory hierarchies, offering high
integration density, larger capacity, zero standby power and good resilience
to soft errors. The recent research progress of various NVMs, e.g., NAND
flash, PCM, STT-RAM, RRAM, FeRAM, etc., have drawn tremendous attentions from
both academia and industry. Besides developing robust and scalable devices,
the unique characteristics of these NVM technologies, such as read-write
asymmetry, stochastic programming behavior, performance-power-nonvolatility
tradeoff, etc., introduce plenty of opportunities and challenges for novel
circuit designs, architectures, system organizations, and management
strategies. There is an urgent need for technology invention, modeling,
analysis, design and application of these NVMs ranging from circuit design to
system design levels.

IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA) provides a
fantastic opportunity for global nonvolatile memory researchers from different
communities to discuss and exchange knowledge, ideas, and insights, and to
facilitate the establishment of potential collaborations that can speed up the
progress in the design and application of NVMs. An expanded technical program
will be offered in NVMSA 2016 for the audience from academy and industry. The
organizing committee is soliciting papers on various topics related to NVMs
including (but not limited to):

Device/Circuit design of NVMs
– Emerging Non-volatile Memory Circuit Design
– NVM Device Design
– Error correction for NVMs
– Nonvolatile Logic Circuit Design

NVM Architectures and Systems
– Non-volatile Registers
– Non-volatile Memory Architectures
– Non-volatile Cache Design
– NVM-based Neuromorphic Architectures
– NVM-based Storage

NVM Software
– Operating System Support for NVM
– Compiler Optimization for NVM
– NVM-based File Systems
– NVM-based Storage Software
– NVM-based Databases
– NVM Controller Design

NVM Applications
– In-memory Computing
– NVM for Big Data Analytics
– NVM in Mobile Healthcare Applications
– NVM in Wearable Applications
– NVM and the Internet of Things

The topics of NVMSA cover the research and development advances in both
mainstream and emerging NVMs. The event is designed to foster interaction and
presentation of early results, new ideas and speculative directions. Thus,
NVMSA will combine the presentations of the papers accepted from the regular
submissions as well as a number of invited talks from researchers in academia,
technologists from industry, and case studies on the use of NVMs.
Participating authors are invited to submit six-page manuscripts to the
conference. All accepted papers will be published in the conference
proceedings. Conference content will be submitted for inclusion into IEEE
Xplore as well as other Abstracting and Indexing (A&I) databases.
Extensions of some selected papers will be published in a special issue of The
Journal of Systems Architecture: Embedded Software Design.

Associated Conference: The 22nd IEEE International Conference on
Embedded and Real-Time Computing Systems and Applications (RTCSA 2016)