Call for Nominations: ACM SIGARCH Student Scholarships for ACM’s Celebration of 50 Years of the ACM Turing Award

ACM SIGARCH Student Scholarships for ACM’s Celebration of 50 Years of the ACM Turing Award
June 23-24, 2017
San Francisco, CA, USA

Nomination Deadline: 3 March 2017

ACM SIGARCH has a limited number of scholarships to award to worthy students to attend the Celebration of 50 Years of the ACM Turing Award 23-24 June 2017 at the Westin St. Francis in San Francisco, CA. Each scholarship includes 2 nights at the Westin St. Francis Hotel in San Francisco and up to $900 to help offset the cost of travel and subsistence (Students will receive a check from ACM upon submission of receipts for travel). Program details can be found here:

– Submission Deadline: 3 March 2017
– Notification of Awards: 10 March 2017
– ACM Turing Centenary Celebration 23-24 June 2017

A nominee must be a student in good standing who is actively pursuing research in computer architecture and an ACM SIGARCH student member/member at the time of the Turing Celebration.

A nomination should consist of the following items:
1. Name, address, phone number, and email address of the person making the nomination (the nominator).
2. Name, address, phone number, and email address of the candidate for whom the scholarship is recommended (the nominee).
3. A short statement (200-500 words) summarizing the nominee’s standing in graduate school (include years in school and estimated years to completion) and explaining why the nominee deserves the scholarship (information on membership in underrepresented groups is welcome and encouraged).

Nominations and questions should be submitted to:
Natalie Enright Jerger, Executive Committee, ACM SIGARCH

SIGARCH statement on the US travel ban

SIGARCH expresses concerns about the presidential executive order restricting entry into the USA.

The SIGARCH executive committee shares the concerns of its parent organization, ACM, about the implications of the USA president’s executive order restricting entry of certain foreign nationals to the USA. These restrictions will not only affect scientists and members of our community who live outside of the USA, but they also impact the ability of many within the USA, in particular students, to travel. SIGARCH does not believe in, nor does it endorse, discrimination based on race, gender, faith, nationality or culture and is fully committed to its mission in spite of these restrictions. SIGARCH will be working on policies to best address this situation. Meanwhile, we strongly encourage all our sponsored events to provide support (e.g., technologies for remote participation) to maximize inclusive participation of our broader scientific community worldwide. Proposals for financial support towards this end should be submitted to the SIGARCH treasurer and will be considered on a case by case basis. We encourage event organizers to share their efforts and experiences and welcome all input and feedback at

Call for Papers: The 2nd Cache Replacement Championship

2nd Cache Replacement Championship (CRC-2)
co-located with ISCA
Toronto, Canada
June 25, 2017

Feb 6: Competition simulator (framework) released on the website
April 14: Submissions due (300 word abstract, prefetching module, 4 page write-up)
April 28: Author notification

The goal for this competition is to compare different cache replacement algorithms for a last level cache in a common framework. Replacement algorithms will be evaluated for both private and shared last level caches with and without a data cache prefetcher. The algorithms must be implemented within a fixed storage budget as specified in the competition rules. Submissions will be evaluated based on their performance using the framework provided by the organizing committee.

Submissions will be evaluated for the following four configurations:
1. Single core with 2 MB LLC w/o a prefetcher.
2. Single core with 2 MB LLC w/ prefetcher.
3. A 4-core configuration with 8 MB of shared LLC w/o prefetcher.
4. A 4-core configuration with 8 MB of shared LLC w/ prefetcher.

The champion (best geomean speedup versus baseline across all traces and configurations) will receive a trophy commemorating his/her triumph. In addition to the top performance champion, the program committee will select the best technical paper from all submissions, which does not necessarily have to be that of the champion.

Sign up for the mailing list by sending an empty email to:

We will announce the availability of the competition framework on the mailing list and the website.

All source code, write-ups and performance results will be made publicly available through the CRC website.

PC Chair:
Paul V. Gratz, Texas A&M University

Organizing Committee Chair:
Jinchun Kim, Texas A&M University

Organizing Committee:
Alaa R. Alameldeen, Intel
Aamer Jaleel, NVIDIA
Seth Pugsley, Intel
Chris Wilkerson, Intel

Program Committee:
Mike Ferdman, Stony Brook University
Daniel Jimenez, Texas A&M University
Moinuddin Qureshi, Georgia Tech University
Eric Rotenburg, North Carolina State University
Carole-Jean Wu, Arizona State University
Akanksha Jain, University of Texas at Austin

Submission Chair:
Gino Chacon, Texas A&M University

Call for Participation: WAX 2017

Workshop on Approximate Computing Across the Stack (WAX 2017)
co-located with ASPLOS 2017.
Xi’an, China
April 9, 2017

WAX, the workshop on approximate computing, will be co-located again with ASPLOS this year. WAX is a venue for discussion computer systems that trade off accuracy for efficiency in all forms.

You can participate in WAX by submitting a short peer-reviewed position paper, giving a lightning talk, or suggesting discussion topics. Position papers are due on February 20.

Full CFP available at

Call for Papers: ISLPED 2017

IEEE/ACM International Symposium On Low Power Electronics And Design (ISLPED)
Taipei, Taiwan
July 24-26, 2017

Abstract registration: Feb 27, 2017, 11:59pm Pacific Standard Time
Full paper submission: Mar 6, 2017, 11:59pm Pacific Standard Time
Notification of paper acceptance: May 3, 2017
Camera-ready version due: June 1, 2017

The International Symposium on Low Power Electronics and Design (ISLPED) is the premier forum for presentation of innovative research in all aspects of low power electronics and design, ranging from process technologies and analog/digital circuits, simulation and synthesis tools, system-level design and optimization, to system software and applications. Specific topics include, but are not limited to, the following three main tracks and sub-areas:

1. Technology, Circuits, and Architecture
1.1. Technologies
1.2. Circuits
1.3. Logic and Architecture

2. CAD, system, and software
2.1. CAD Tools and Methodologies
2.2. Systems and Platforms
2.3. Software and Applications

3. Industrial Design Track

Submissions should be full-length papers of up to 6 pages (PDF format, double-column, US letter size, using the ACM Conference format, available at including all illustrations, tables, references, and an abstract of no more than 250 words. Submissions must be anonymous. Submissions exceeding 6 pages or identifying the authors, either directly or through explicit references to their prior work, will be automatically rejected. More information about paper submission can be found at

General Co-Chairs
Chia-Lin Yang, NTU
David Garrett, Broadcom

Program Co-Chairs
Thomas Wenisch, Univ. Michigan
Jaydeep Kulkarni, Intel

Call For Papers: MICRO 2017

The 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-50)
Boston, USA
Oct 14-18, 2017

Abstracts due: March 28, 2017
Papers due: April 4, 2017
Response period: June 1-14, 2017
Author notification: July 5, 2017

The International Symposium on Microarchitecture (MICRO) is the premier forum for the presentation and discussion of new ideas in microarchitecture, compilers, hardware/software interfaces, and design of advanced computing and communication systems. The goal of MICRO is to bring together researchers in the fields of microarchitecture, compilers, and systems for technical exchange. The MICRO community has enjoyed having close interaction between academic researchers and industrial designers — we aim to continue and strengthen this longstanding tradition at the 50th MICRO.

We invite original paper submissions related (but not limited) to the following topics:
– Processor, memory, interconnect, and storage architectures.
– Hardware, software, and hybrid techniques for improving system performance, energy-efficiency, cost, complexity, predictability, quality of service, reliability, dependability, security, scalability, programmer productivity, etc.
– Architectures for instruction-level, thread-level, and memory-level parallelism: superscalar, VLIW, data-parallel, multithreaded, multicore, manycore, etc.
– Compiler and microarchitectural techniques for parallelism (ILP, TLP, MLP).
– Low-power, high-performance, and cost/complexity-efficient architectures.
– Architectures for emerging platforms, including smartphones, cloud/datacenter, etc.
– Architectures and compilers for embedded processors, DSPs, GPUs, ASIPs (network processors, multimedia, wireless, deep learning, neuromorphic, etc.).
– Advanced software/hardware speculation and prediction schemes.
– Microarchitecture techniques to better support system software, programming languages, programmability, and compilation.
– Microarchitecture modeling and simulation methodology.
– Insightful experimental and comparative evaluation and analysis of existing microarchitectures, hardware/software mechanisms and workloads.

News: Twitter @MicroArchConf

Call for Workshops and Tutorials: MICRO 2017

IEEE/ACM International Symposium on Microarchitecture
Boston, USA
Oct 14-15, 2017

Submission Deadline: May 12, 2017
Notification Date: May 19, 2017

Proposals should be one to two pages and must include the following information:
1. Title of the Workshop / Tutorial.
2. Organizers and their affiliations (including short bios).
3. Expected duration of the workshop/tutorial; i.e., half day or full day.
4. If the workshop/tutorial was previously held, provide the location (i.e., which conference), date, number of published papers (if any), and number of attendees at the last event.
5. If workshop proposal, provide sample call for papers, including the workshop main topics.
6. If tutorial proposal, provide the abstract of the tutorial.

Submit workshop and tutorial proposals to

Call for Papers: GreenMetrics 2017

GreenMetrics 2017 Workshop
in conjunction with ACM SIGMETRICS 2017
Urbana-Champaign, IL, USA
June 5, 2017

Paper Submission: Monday, March 27, 2017 (hard deadline)
Author Notification: Wednesday, April 19, 2017
Final Versions Due: Monday, May 22, 2017
Workshop: Monday, June 5, 2017
Final Versions for PER Due: Date TBD

Sustainability is a topic of increasing importance in modern society. The primary objective of this workshop is to explore how improvements to or new uses of Information and Communication Technology (ICT) can improve the environmental, economic and/or social sustainability of ICT systems, networks, and applications and of non-ICT processes (e.g., quantify the reduction in cost or carbon emissions from using tele-presence services instead of travel).

Topics of interest fall broadly into three main areas:
– Designing sustainable ICT: Such work includes research measuring, evaluating, or designing energy efficient systems in data centers, networking and communication protocols, etc.
– ICT for sustainability: Such work includes research proposing new uses of ICT to improve the environmental, economic, and/or social sustainability of non-ICT processes.
– Building a smarter, more sustainable electricity grid: Such work includes research addressing the challenges (both engineering and economic) that come from incorporating increasing penetration of renewable energy into the grid, demand-response techniques, and smart-metering.

This workshop is intended to bring together researchers from the (traditional) SIGMETRICS and Performance communities with researchers and practitioners in the three areas above, to exchange technical ideas and experiences on issues related to sustainability and ICT. The workshop will include a mixture of invited talks and presentations of accepted papers, and will serve as a forum for the SIGMETRICS communities to apply their techniques to this emerging and important area.

An award will be presented for the best student paper, and we will have an exciting series of keynote talks, including talks by Peter W. Sauer (UIUC), David Irwin (UMASS Amherst), and Thomas Wenisch (UMichigan).

In order to be inclusive of authors from different communities Greenmetrics will have two options for paper submissions. Authors may either submit full papers or extended abstracts. Full papers are allowed to be six double-column pages, while extended abstracts are allowed to be up to three double-column pages. Both types of submissions should be in the standard ACM format, and both types of submissions will be reviewed. While full papers must be either new material or a survey article, extended abstracts may summarize recent submissions to other venues (either conferences or journals). Thus, we hope that authors will submit extended abstracts in order to present recent work from other communities to the Sigmetrics community.

Submissions must be submitted electronically in printable PDF form, via the GreenMetrics 2017 submission site:

Submissions will be reviewed by the GreenMetrics program committee, from which a number of papers will be selected for presentation at the workshop. The accepted papers will be published in ACM SIGMETRICS Performance Evaluation Review (PER). Authors of accepted papers grant permission to ACM to publish the paper in PER and the ACM digital library. Authors do retain the copyright of their paper.


Niklas Carlsson, Linkoping University (
Zhenhua Liu, Stony Brook University (
Thu Nguyen, Rutgers University (
Catherine Rosenberg, University of Waterloo <200e>(
Adam Wierman, Caltech (

Program Committee:
Danilo Ardagna, Politecnico di Milano
Martin Arlitt, Hewlett Packard Labs
Subhonmesh Bose, Illinois
Abhishek Chandra, University of Minnesota
Lydia Y. Chen, IBM Zurich Research Laboratory
Yuan Chen, Hewlett Packard Labs
Emiliano Dall’Anese, NREL
György Dan, KTH Royal Institute of Technology
Florian Dorfler, Swiss Federal Institute of Technology (ETH Zurich)
Derek Eager, University of Saskatchewan
Nicolas Gast, INRIA
Yashar Ghiassi-Farrokhfal, Erasmus University Rotterdam
Emir Halepovic, AT&T
Nidhi Hegde, Nokia
Longbo Huang, Tsinghua University
Guillaume Jourjon, DATA61
Srinivasan Keshav, University of Waterloo
Diwakar Krishnamurthy, University of Calgary
Na Li, Harvard
Cue Liu, McGill
Steven Low, Caltech
Manish Marwah, Hewlett Packard Labs
Arif Merchant, Google
Michela Meo, Politecnico di Torino, Italy
Ram Rajagopal, Stanford
Lei Rao, Huawei US R&D
Cristina Rottondi, IDSIA
Weisong Shi, Wayne State
Ramesh Sitaraman, Umass
Anand Sivasubramaniam, Pennsylvania State University
Christopher Stewart, Ohio State University
Massimo Tornatore, Politecnico di Milano, Italy
Jia Wang, AT&T Research

Call for papers: ASAP 2017

28th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)
Seattle, WA, USA
July 10-12, 2017

Submission deadline: April 3, 2017
Notification of acceptance: May 12, 2017
Camera ready: June 2, 2017

The ASAP 2017 conference will cover the theory and practice of application-specific systems, architectures and processors. We will build upon traditional strengths of the conference in areas such as computer arithmetic, cryptography, compression, signal and image processing, network processing, reconfigurable computing, and all types of hardware accelerators. We especially encourage submissions in the following areas:

– Big data analytics: extracting and correlating information from large-scale semi-structured and unstructured data using application-specific systems.
– Machine learning: specialized platforms or hardware-optimized algorithms to improve the performance or efficiency of model creation and/or prediction.
– Scientific computing: architectures and algorithms that address scientific applications requiring significant computing power and design customization (bioinformatics, climate modeling, astrophysics, seismology, etc.).
– Industrial computing: systems and architectures for providing high- throughput or low latency in various industrial computing applications.
– System security: cryptographic hardware architectures, security processors, countermeasures against side-channel attacks, and secure cloud computing.
– Heterogeneous systems: applications and platforms that exploit heterogeneous computing resources, including FPGAs, GPUs, or CGRAs.
– Design space exploration: methods for customizing and tuning application-specific architectures to improve efficiency and productivity.
– Platform-specific architectures: novel architectures for exploiting specific compute domains such as smartphones, tablets, and data centers, particularly in the context of energy efficiency.

ASAP 2017 will accept 8-page full papers for oral presentations and 4-page short papers for short oral or poster presentations, with a double-blind review process. An online submission page will be made available on the website and will include detailed guidelines and links to formatting templates.

General Chair:
Ken Eguro, Microsoft Research

Program Chair:
Ryan Kastner, University of California, San Diego

Call for Papers: PACT 2017

26th International Conference on Parallel Architectures & Compilation Techniques
Portland, Oregon, USA
September 9-13, 2017

Paper Deadline: March 14, 2017
Author Response Period: May 3-6, 2017
Author Notification: May 24, 2017
Camera Ready Final Papers: July 19, 2017

The purpose of PACT 2017 is to bring together researchers from architecture, compilers, applications and languages to present and discuss innovative research of common interest.

PACT started as a Data Flow Workshop in conjunction with ISCA 1989 but quickly evolved into a unique venue at the intersection of classical parallel architecture and compilers.

Recently, PACT widened its scope to include insights useful for the design of machines and compilers from applications such as, but not limited to, machine learning, data analytics and computational biology.

PACT solicits novel papers, workshops, tutorials, and entries to an ACM student research competition on a broad range of topics that include, but are not limited to:
– Parallel architectures and computational models
– Compilers and tools for parallel computer systems
– Multicore, multithreaded, superscalar, and VLIW architectures
– Compiler/hardware support for hiding memory latencies
– Support for correctness in hardware and software
– Reconfigurable parallel computing
– Dynamic translation and optimization
– I/O issues in parallel computing and their relation to applications
– Parallel programming languages, algorithms and applications
– Middleware and run time system support for parallel computing
– Application-specific parallel systems
– Applications and experimental systems studies of parallel processing
– Relevant aspects of distributed computing and mobile computing
– Heterogeneous systems using various types of accelerators
– Insights from modern parallel applications such as, but not limited to, machine learning, data analytics, and computational biology for the design of parallel architectures and compilers

Submitted papers will be evaluated on technical merits and clarity of presentation. Papers must contain sufficient information and be organized in such a way that their technical contribution and significance can be understood by a wide audience of computer scientists.

Submitted papers must be original material that has not been previously published in another conference or journal, nor is currently under review by another conference or journal. Papers are to be submitted for double-blind review. This means that author names as well as hints of identity are to be removed from the submitted paper.

Authors of accepted papers will be invited to formally submit their supporting materials to the Artifact Evaluation Committee. The task of this committee is to assess how the artifacts support the work described in the papers. Submission is voluntary. Papers that go through the artifact evaluation process successfully will receive a seal of approval which will be printed on the first page of the papers in the proceedings.

General Chair:
Ravi Iyer, Intel

Program Chair:
David Padua, University of Illinois

Program Committee:
Gagan Agrawal Ohio State University
Srinivas Aluru Georgia Tech
Rafael Asenjo Universidad de Malaga
Michael Burke Rice University
Albert Cohen INRIA
Ron Cytron Washington University
Michel Dubois University of Southern California
Babak Falsafi EPFL
Franz Franchetti Carnegie Mellon University
David Gregg Trinity College Dublin
Todd Gamblin Lawrence Livermore National Laboratory
Angeles Navarro Universidad de Malaga
R. Govindarajan Indian Institute of Science, Bangalore
Ananth Grama Purdue University
Rajiv Gupta University of California, Riverside
Kei Hiraki The University of Tokyo
Antony Hosking The Australian National University / Data61
Francois Irigoin MINES Paris Tech
George Karypis University of Minnesota
Andreas Kloeckner University of Illinois at Urbana-Champaign
Jaejin Lee Seoul National University
Andrew Lumsdaine Pacific Northwest National Lab and Univ of Washington
Saeed Maleki Microsoft Research
Allen Malony University of Oregon
Yunheung Paek Seoul National University
Keshav Pingali The University of Texas at Austin
Sanjay Rajopadhye Colorado State University
Lawrence Rauchwerger Texas A&M University
P. (Saday) Sadayappan Ohio State University
Xipeng Shen North Carolina State University
Cristina Silvano Politecnico di Milano
Edgar Solomonik University of Illinois at Urbana-Champaign
Per Stenstrom Chalmers University of Technology

ACM, IEEE Computer Society, IFIP