Call for contributions: FPL PhD Forum and Demo Night

Submitted by Mirjana Stojilovic
http://www.fpl2016.org

26th International Conference on Field-Programmable Logic and Applications (FPL)
Aug 29 – Sep 2, 2016
Lausanne, Switzerland
 

IMPORTANT DATES:
PhD Forum and Demo Night proposals deadline: May 8, 2016
Notifications: June 15, 2016
 

CALL FOR CONTRIBUTIONS TO PhD FORUM

FPL 2016 PhD Forum is tailored for PhD students in two ways: Firstly,
it is an excellent occasion for PhDs to present their work in progress
or preliminary results, and receive early feedback from other
researchers in the domain. Secondly, it is a unique opportunity for
PhD students who are finishing their studies to give a broad overview
of their work and draw attention to it from both the academic and
industrial worlds.

PhD Forum authors are invited to submit 2-page papers using the format
of FPL 2016 regular papers. PhD Forum papers should include clear
descriptions of thesis motivation, objectives, problem definition,
addressed solutions, current status, and planned work. Contributions
based on preliminary results or on work in progress are particularly
encouraged. Accepted PhD Forum papers will be included in the
conference proceedings and presented at a special poster session.
Prior to this session, presenters will be offered the opportunity to
draw attention to their posters through a short “elevator pitch”
(2-minute presentation).
 

CALL FOR CONTRIBUTIONS TO DEMO NIGHT

FPL 2016 Demo Night event is an excellent opportunity for conference
participants to demonstrate and disseminate their work, to increase
their visibility, and interact with attendees. Demonstrations may
include commercial and academic research-oriented tools, platforms,
systems, and more. The event will take place on one of the conference
evenings. Hors d’oeuvres and drinks will be offered to all attendees.

Demo Night presenters are invited to submit 1-page abstracts using the
same format as FPL 2016 regular papers. A cover page should be added
to the submission and should contain the following information:
– Demo title.
– Names and affiliations of all authors.
– Description of the main objectives and relevance of the demo to the
FPL community.
– Short biographies of demo presenters.
– Any logistical requirements the demonstration may have.

The 1-page abstract should include demo title, names and affiliations
of all authors, and an abstract of the demo. The authors of the
accepted demos will be asked to prepare a poster for the Demo Night.
All demo posters will be published on the FPL 2016 web page and the
abstracts will be included in the conference proceedings.
 

ORGANIZERS
FPL PhD Forum and Demo Night chairs:
Mirjana Stojilović, University of Applied Sciences Western Switzerland
Yann Thoma, University of Applied Sciences Western Switzerland

Call for Participation: ISPASS 2016

Submitted by Erik Hagersten
http://www.ispass.org/ispass2016
April 17 to April 19, 2016

Submitted by Erik Hagersten
http://www.ispass.org/ispass2016

The 17th International Symposium on Performance Analysis of
Systems and Software (ISPASS)

Uppsala, Sweden

April 17: Workshops/Tutorials (3 workshops and 4 tutorial)
April 18-19: Conference (including 3 keynotes)

Early registration: March 18
Hotel reservation: March 18

The name says it all: IEEE International Symposium on Performance Analysis of
Systems and Software. The focus is on performance-related problems, solutions,
methods and tools for software and system performance and power analysis
and optimisation.

After 16 years in the US, the ISPASS conference is now moving “abroad” for
the first time.

General Chair: Erik Hagersten, Uppsala University
Program Chair: Andreas Moshovos, University of Toronto

Call for Nominations: 2016 IEEE TCCA Young Computer Architect Award

Submitted by Kunle Olukotun

Submitted by Kunle Olukotun

The 2016 IEEE TCCA Young Computer Architect Award

Nomination deadline: April 15, 2016
 

The IEEE TCCA Young Computer Architect Award recognizes outstanding research
contributions by an individual in the field of Computer Architecture, who
received his/her PhD degree within the last 6 years. The Award will be
presented at the Awards Banquet at the 2016 International Symposium on
Computer Architecture (ISCA). The IEEE Computer Society administers the award.

Eligibility: The award is open to any individual who has completed his/her PhD
degree after April 15, 2010 (within last 6 years). At the discretion of the
awards committee, eligibility may be adjusted for documented family-related or
medical leaves from employment. The winner of the award will be someone who
has made an outstanding, innovative research contribution or contributions to
the field of Computer Architecture.

NOMINATION PROCESS:
Anyone can nominate a candidate (but no self-nominations). The following
information must be provided at the time of nomination:

1. Name/email of person making the nomination.

2. Name/email of candidate for whom the award is recommended.

3. A statement by the nominator (maximum of 500 words long) as to why
the nominee deserves the award. As the award is for outstanding contributions
in research, the statement and supporting letters should address the
contributions and why they are both outstanding and significant.

4. CV of the candidate.

5. The names and email addresses of two persons who the nominator has
contacted to supply supporting letters.

All materials, including the two supporting letters, should be sent to the Chair
of the Selection Committee by April 15, 2016. The award will be presented at
the Awards Banquet of the 43rd International Symposium on Computer
Architecture (ISCA) in Seoul, Korea, June 18-22, 2016.

SELECTION COMMITTEE:
Lieven Eeckhout (Ghent University)
Onur Mutlu (Carnegie Mellon University)
Kunle Olukotun (Stanford University) – Chair (kunle@stanford.edu)

PAST WINNERS:
2015: Prof. Ronald Dreslinski, The University of Michigan, in recognition of
outstanding research contributions in computer architectures for emerging
low-power circuit techniques

2014: Prof. Engin Ipek, The University of Rochester, in recognition of
outstanding research contributions for computer architectures that leverage
emerging technologies

2013: Prof. Luis Ceze, The University of Washington, in recognition of
outstanding research contributions for improving multi-core programmability
and correctness

2012: Prof. Karthikeyan Sankaralingam, The University of Wisconsin, in
recognition of outstanding contributions in the field of computer architecture
in both research and education

2011: Prof. Onur Mutlu, Carnegie Mellon University, in recognition of
outstanding contributions in the field of computer architecture in both
research and education

Available Now: IEEE Micro Special Issue on Near-Data Processing

Submitted by Lieven Eeckhout
http://online.qmags.com/MIC0116?sessionID=6D82D319BF01A05D0C8C0796A&cid=3196036&eid=19756#pg1&mode2

Submitted by Lieven Eeckhout
http://online.qmags.com/MIC0116?sessionID=6D82D319BF01A05D0C8C0796A&cid=3196036&eid=19756#pg1&mode2
IEEE Micro Special Issue on Near-Data Processing

The Jan/Feb 2016 IEEE Micro Special Issue on Near-Data Processing,
guest edited by Rajeev Balasubramonian (University of Utah) and Boris Grot
(University of Edinburgh), is now available. The issue includes expert opinions
and position statements on near-data processing along with in-depth articles.
The issue also features two testimonials on MICRO Test-of-Time Awards.

Call for Nominations: ACM SIGARCH Distinguished Service Award

Submitted by Natalie Enright Jerger
http://www.sigarch.org/awards/acm-sigarch-distinguished-service-award/

Submitted by Natalie Enright Jerger
http://www.sigarch.org/awards/acm-sigarch-distinguished-service-award/

ACM SIGARCH Distinguished Service Award

Nomination Deadline: April 8, 2016
 

This annual award is presented to an individual who has contributed important service to the computer architecture community.

Recipients receive a memento engraved with their name along with a $1000 honorarium. The award is presented by the SIGARCH chair at ISCA during ISCA’s award presentation session. The award recipient also receives up to $2000 towards support for travel costs, including airfare, hotel, and conference registration for ISCA. The recipient is listed with a citation for their award on the SIGARCH Distinguished Service Award web page. The list of past award
recipients is at http://www.sigarch.org/awards/acm-sigarch-distinguished-award-past-winners/

The selection committee consists of 3 or more members and is appointed by the
SIGARCH chair. The committee typically includes recent recipients of the award
and current SIGARCH executive committee members. The committee solicits
nominations from the computer architecture community in a variety of ways
including announcements in SIGARCH’s newsletter and postings on appropriate
newsgroups and websites. The committee considers all external nominations, plus
any internal nominations from members of the committee, in the context of the
nominees’ specific and general service contributions to the computer
architecture community.

NOMINATION PROCESS:

Nominations can be submitted at any time to the committee chair (Norm Jouppi,
jouppi@acm.org). Nominations submitted by April 8th will be considered for this
year’s award. A nomination for the distinguished service award that is not
awarded will remain valid for 3 years.

Each nomination should consist of the following items:
– Name, address, phone number, and email address of the person making the
nomination (the nominator).
– Name, address, phone number, and email address of the candidate for whom
an award is recommended (the nominee).
– A short statement (200-500 words) explaining why the nominee deserves the
award in question.
– Names and email addresses of 4-7 people who the nominator believes will
support the nomination.
– The awards committee will ask some of these people for their opinions.

Self-nominations are not allowed.

The 2016 selection committee is:
– Norman P. Jouppi (chair), Google, jouppi@acm.org
– Trevor Mudge,
 University of Michigan, 
tnm@eecs.umich.edu
– David Brooks,
 Harvard University, dbrooks@eecs.harvard.edu

Call for Papers: NVMSA 2016

Submitted by Onur Mutlu
https://sites.google.com/a/camelab.org/nvmsa-2016/
April 1, 2016

Submitted by Onur Mutlu
https://sites.google.com/a/camelab.org/nvmsa-2016/

The 4th IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA)
Daegu, Korea
August 17-19, 2016
 

IMPORTANT DATES:
April 1: Abstract Submission Deadline
April 14: Paper Submission Deadline
June 1: Acceptance notification
June 12: Camera ready
 

Non-Volatile memory (NVM) technologies have demonstrated great potential to
improve many aspects of present and future memory hierarchies, offering high
integration density, larger capacity, zero standby power and good resilience
to soft errors. The recent research progress of various NVMs, e.g., NAND
flash, PCM, STT-RAM, RRAM, FeRAM, etc., have drawn tremendous attentions from
both academia and industry. Besides developing robust and scalable devices,
the unique characteristics of these NVM technologies, such as read-write
asymmetry, stochastic programming behavior, performance-power-nonvolatility
tradeoff, etc., introduce plenty of opportunities and challenges for novel
circuit designs, architectures, system organizations, and management
strategies. There is an urgent need for technology invention, modeling,
analysis, design and application of these NVMs ranging from circuit design to
system design levels.

IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA) provides a
fantastic opportunity for global nonvolatile memory researchers from different
communities to discuss and exchange knowledge, ideas, and insights, and to
facilitate the establishment of potential collaborations that can speed up the
progress in the design and application of NVMs. An expanded technical program
will be offered in NVMSA 2016 for the audience from academy and industry. The
organizing committee is soliciting papers on various topics related to NVMs
including (but not limited to):

Device/Circuit design of NVMs
– Emerging Non-volatile Memory Circuit Design
– NVM Device Design
– Error correction for NVMs
– Nonvolatile Logic Circuit Design

NVM Architectures and Systems
– Non-volatile Registers
– Non-volatile Memory Architectures
– Non-volatile Cache Design
– NVM-based Neuromorphic Architectures
– NVM-based Storage

NVM Software
– Operating System Support for NVM
– Compiler Optimization for NVM
– NVM-based File Systems
– NVM-based Storage Software
– NVM-based Databases
– NVM Controller Design

NVM Applications
– In-memory Computing
– NVM for Big Data Analytics
– NVM in Mobile Healthcare Applications
– NVM in Wearable Applications
– NVM and the Internet of Things

The topics of NVMSA cover the research and development advances in both
mainstream and emerging NVMs. The event is designed to foster interaction and
presentation of early results, new ideas and speculative directions. Thus,
NVMSA will combine the presentations of the papers accepted from the regular
submissions as well as a number of invited talks from researchers in academia,
technologists from industry, and case studies on the use of NVMs.
Participating authors are invited to submit six-page manuscripts to the
conference. All accepted papers will be published in the conference
proceedings. Conference content will be submitted for inclusion into IEEE
Xplore as well as other Abstracting and Indexing (A&I) databases.
Extensions of some selected papers will be published in a special issue of The
Journal of Systems Architecture: Embedded Software Design.

Associated Conference: The 22nd IEEE International Conference on
Embedded and Real-Time Computing Systems and Applications (RTCSA 2016)

Call for Papers: IEEE Micro General Interest 2016

Submitted by jayvant anantpur
https://sites.google.com/site/ieeemicro/call-for-papers/2016-cfp—general-interest-papers

Submitted by jayvant anantpur
https://sites.google.com/site/ieeemicro/call-for-papers/2016-cfp—general-interest-papers

IEEE Micro General Interest 2016

IEEE Micro seeks general-interest submissions for publication in upcoming 2016
issues. The submissions should present the design, performance, or application
of microcomputer and microprocessor systems. Summaries of work in progress
and descriptions of recently completed work are most welcome, as are tutorials
and position statements.

IEEE Micro is a bimonthly magazine of the IEEE Computer Society that reaches
an international audience of computer designers, system integrators, and users.
IEEE Micro publishes 6 to 8-page papers that are slightly less technical and
less quantitative than top-conference and archival journal papers, while being
insightful, slightly more qualitative, with a high tutorial value, and up to
date with current trends. IEEE Micro attracts a broad readership among both
academics and practitioners who want to keep up with new results and trends in
the field of computer architecture.

Areas of interest include, but are not limited to:
– Processor, memory, and storage systems architecture
– Parallel and multicore systems
– Data-center scale computing
– Architectures for handheld and mobile devices
– Application-specific, reconfigurable, or embedded architectures
– Heterogeneous and accelerator-based architectures
– Neuromorphic computing architectures
– Architectures for security and virtualization
– Power and energy efficient architectures
– Interconnection networks
– Instruction, thread, and data-level parallelism
– Dependable architectures
– Architectural support for programming productivity
– Network processor and router architectures
– Architectures for emerging technologies and applications
– Effect of circuits and technology on architecture
– Architecture modeling and simulation methodology
– Performance evaluation and measurement of real systems
– Design of high-performance and low-power chips

SUBMISSION PROCEDURE:
Log onto IEEE CS Manuscript Central (https://mc.manuscriptcentral.com/micro-cs)
and submit your manuscript. Please direct questions to the IEEE Micro magazine
assistant (micro-­ma@computer.org) regarding the submission site. For the
manuscript submission, acceptable file formats include Microsoft Word and PDF.
Manuscripts should not exceed 5,000 words including references, with each
average­ size figure counting as 250 words and each average-size table counting
as 150 words toward this limit. Please include all figures and tables, as well
as a cover page with author contact information (name, postal address, phone,
fax, and e­mail address) and a 200­-word abstract. Submitted manuscripts must
not have been previously published or currently submitted for publication
elsewhere, and all manuscripts must be cleared for publication. All previously
published papers must have at least 30% new content compared to any
conference (or other) publication. Accepted articles will be edited for
structure, style, clarity, and readability. For more information, please visit the
IEEE Micro Author Center (http://www2.computer.org/portal/web/peerreviewmagazines/acmicro).

The submission site is continuously open. Papers of general interest appear in
upcoming issues as space allows, or are grouped in the Nov/Dec 2016 issue.

Questions?
Contact the Editor-in-Chief, Lieven Eeckhout, at lieven.eeckhout@ugent.be

Call for papers: WDDD 2016

Submitted by Karu Sankaralingam
https://sites.google.com/site/iscawddd/
June 19, 2016

Submitted by Karu Sankaralingam
https://sites.google.com/site/iscawddd/
12th Annual Workshop on Duplicating, Deconstructing and Debunking

12th Annual Workshop on Duplicating, Deconstructing and Debunking (WDDD)
Seoul, S. Korea
June 19, 2016
 

IMPORTANT DATES:
Abstract Submission: April 20, 2016
Paper Submission: April 22, 2016
Acceptance: May 14, 2016
Final Version: June 10, 2016
 

WDDD provides the computer systems research community a forum for work that
validates or duplicates earlier results; deconstructs prior findings by
providing greater, in-depth insight into causal relationships or correlations;
or debunks earlier findings by describing precisely how and why proposed
techniques fail where earlier successes were claimed, or succeed where failure
was reported.

Traditionally, computer systems research conferences have focused almost
exclusively on novelty and performance, neglecting an abundance of interesting
work that lacks one or both of these attributes. A significant part of
research–in fact, the backbone of the scientific method–involves independent
validation of existing work and the exploration of strange ideas that never
pan out. This workshop provides a venue for disseminating such work in our
community. Published validation experiments strengthen existing work, while
thorough comparisons provide new dimensions and perspectives. Studies that
refute or correct existing work also strengthen the research community, by
ensuring that published material is technically correct and has sound
assumptions. Publishing negative or strange or unexpected results will allow
future researchers to learn the hard lessons of others, without repeating
their effort.

This workshop will set a high scientific standard for such experiments, and
will require insightful analysis to justify all conclusions. The workshop will
favor submissions that provide meaningful insights, and identify underlying
root causes for the failure or success of the investigated technique.
Acceptable work must thoroughly investigate and communicate why the proposed
technique performs as the results indicate. WDDD has a unique tradition of
asking the original paper authors to provide a follow-up comment after the
WDDD paper has been presented, where appropriate. The follow-up comment may
take the form of a rebuttal or additional insight from the original authors.

WORKSHOP SCOPE:
In general, any topic that is of interest to computer architecture conferences
and related systems areas are of potential interest for WDDD, so long as the
paper is in the spirit of the themes of Duplication, Deconstruction, and/or
Debunking.

Topics of interest:
– Independent validation of earlier results with meaningful analysis
– In-depth analysis and sensitivity studies that provide further insight into
earlier findings, or identify key parameters or assumptions that affect the
results
– Studies that refute earlier findings, with clear justification and explanation
– Negative results for ideas that intuitively make sense and should work, along
with explanations for why they do not
– Validation/refutation of controversial advertising claims by industrial
competitors

SUBMISSION GUIDELINES:
Submit a manuscript of up to 10 pages in two-column format by April 22, 2016
using the submission website. https://easychair.org/conferences/?conf=wddd16

ORGANIZERS:
Murali Annavaram, USC
Karu Sankaralingam, University of Wisconsin – Madison
David Brooks, Harvard University
Gabriel Loh, AMD Research

Call for Participation: SELSE 2016

Submitted by William H. Robinson
http://www.selse.org
March 29 to March 30, 2016

Submitted by William H. Robinson
http://www.selse.org

The 12th IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE 2016)
Austin, TX, USA
March 29 – 30, 2016
 

Early registration deadline: March 14th, 2016.

Keynote speakers:
SELSE 2016 will feature three keynote speeches by experts from
academia and industry.
– Dr. Krishna V. Palem, Rice University
Can the end of Moore’s Law result in new opportunities for computing?
– Dr. Nirmal Saxena, NVIDIA
Autonomous car is the new driver for resilient computing and
design-for-test.
– Dr. Martin Roetteler from Microsoft Research
Quantum error correction and quantum algorithmic discovery

Panel Discussion:
We will have a very interesting panel on the topic of approximate computing
with experts from academia and industry. The panel discussion will explore
opportunities and challenges of approximate computing in the field of
reliability.

Accommodations:
Please do not forget to book your hotels early, as the hotel prices can
increase closer to the SELSE dates. You can find a list of nearby hotels
on the SELSE web page.

Travel grants:
We are very excited to offer, for the first time, travel grants to young
faculties, postdocs, and students. Please refer to SELSE web page for
application instructions. Submit your application by March 12th.

ORGANIZERS:
General Chairs:
Helia Naeimi, Intel
Dan Alexandrescu, iRoC

Program Chairs:
Sudhanva Gurumurthi, IBM/University of Virginia
Mattan Erez, The University of Texas at Austin

Finance Chairs:
Siva Hari, NVIDIA
Daniel Lowell, AMD

Publicity Chairs:
William H. Robinson, Vanderbilt University
Paolo Rech, UFRGS
Yiannakis Sazeides, University of Cyprus

Documents Chairs:
Mehdi Tahoori, Karlsruhe Institute of Technology
Mojtaba Ebrahimi, Karlsruhe Institute of Technology

Austin Industry Liaison:
Indrani Paul, AMD

Webmaster:
Marios Kleanthous, Mesoyios College

Local Arrangements Chair:
Vijay Janapa Reddi, The University of Texas at Austin

Advisors to the Committee:
Sarah Michalak, LANL
Alan Wood, Oracle
Vilas Sridharan, AMD
Adrian Evans, iRoC

Call for Participation: OpenPiton Tutorial

Submitted by David Wentzlaff
http://parallel.princeton.edu/openpiton/ISCA16_tutorial.html

Submitted by David Wentzlaff
http://parallel.princeton.edu/openpiton/ISCA16_tutorial.html

OpenPiton Tutorial
co-located with ISCA 2016
Seoul, S. Korea
June 19, 2016
 

This tutorial will introduce the user to OpenPiton including how to use the
framework to build different designs. The tutorial will introduce the
verification framework (Verilog simulation), how to synthesize an OpenPiton
processor for a Xilinx FPGA board, it will demonstrate booting Linux on an
FPGA version of OpenPiton, it will familiarize users with how to use the
OpenPiton framework to target an ASIC tapeout, and it will show users how to
configure and extend the OpenPiton architecture to enable architecture
research. This tutorial will be hands-on so please bring a laptop.

OpenPiton is an open source framework designed to enable scalable architecture
research prototypes from 1 core to 500 million cores. OpenPiton is the
world’s first open source, general-purpose, multithreaded manycore processor
and framework. OpenPiton leverages the industry hardened OpenSPARC T1 core
with modifications and builds upon it with a scratch-built, scalable uncore
creating a flexible, modern manycore design. In addition, OpenPiton provides
synthesis and backend scripts for ASIC and FPGA to enable other researchers to
bring their designs to implementation. On FPGA, OpenPiton provides a new high
performance memory controller. OpenPiton provides a complete verification
infrastructure of over 8000 tests, is supported by mature software tools, runs
full-stack multiuser Debian Linux, and is written in industry standard
Verilog. Multiple implementations of OpenPiton have been created including a
taped-out 25-core implementation in IBM’s 32nm process and multiple Xilinx
FPGA prototypes.