Call for Participation: Tutorial on Quantum Computing

Tutorial: From Quantum Bits to Quantum Computing
in conjunction with HPCA
Austin, USA
February 5, 2017

Quantum computers hold the promise for solving efficiently important problems in computational sciences that are intractable nowadays by exploiting quantum phenomena such are superposition and entanglement. One of the most famous examples is the factorization of large numbers using Shor’s algorithm. For instance, a 2000-bit number could be decomposed in a bit more than one day using a quantum computer whereas a data center of approx. 400.000 Km2 built with the fastest today’s supercomputer would require around 100 years.

This tutorial will introduce the basic notions of quantum computing and will address the main challenges when building a large-scale quantum computer. The tutorial will provide hands-on exercises based on the QX simulator platform and will allow participants to understand what quantum circuits and quantum gates are.

Topics:
-Overview of quantum computing, as compared to classical computing
-Universal quantum gates and quantum circuits
-Quantum error correction
-Quantum computer architecture
-Exercises writing small quantum circuits using the QX simulation platform

ORGANIZERS:
Koen Bertels, Delft University of Technology, NL
Carmen G. Almudever, Delft University of Technology, NL

Call for Presentations: Systems Support for Big Data Applications

Systems Support for Big Data Applications
https://www.hipeac.net/events/activities/7412/systems-support-for-big-data-applications
in conjuction with HiPEAC Autumn Computing Systems Week
Dublin, Ireland
November 7, 2016

Submission Deadline: October 21, 2016.

We are now living in a world of Big Data. The ability to process and analyse large data sets is revolutionising the way we live, work and socialise. Building software and hardware systems that can process big data with high throughput is thus a critical task for the research community and industry. Hardware and software solutions to address the problem of how to program, optimise and manage Big Data applications form the core topic of this session.

Topics of interest for this session include, but are not limited to, recent results and demonstrations, involving:
– Novel hardware systems for data intensive applications
– Programming languages and models for Big Data applications
– Compilers and tools for Big Data optimisation
– Runtime and operating systems for Big Data applications
– Middleware and software architecture for Big Data
– Big Data applications

If you are interested in giving a presentation, send an email to Vicent Sanz Marco (v.sanzmarco@lancaster.ac.uk) and Pavlos Petoumenos (ppetoume@inf.ed.ac.uk) with a 200-word abstract by Friday, 21st of October, 2016.

Talks from industrial partners are particularly welcome.

Call for Papers: ARCS 2017

30th International Conference on Architecture of Computing Systems (ARCS 2017)
http://arcs2017.itec.kit.edu/
Vienna, Austria
April 3-6, 2017

IMPORTANT DATES:
Paper submission deadline: October 28, 2016
Workshop and tutorial proposals: November 30, 2016
Notification of acceptance: December 21, 2016
Camera-ready papers: January 11, 2017

The ARCS conferences series has over 30 years of tradition reporting leading edge research in computer architecture and operating systems. The focus of the 2017 conference will be on Heterogeneous Node Architectures with Deep Memory Systems. ARCS 2017 will be organized by the Complang Group at the Vienna University of Technology and the CAPP group at the Karlsruhe Institute of Technology (KIT).

Authors are invited to submit original, unpublished research papers on one or more of the following topics:
– Multi-/many-core architectures, memory systems, and interconnect networks
– Programming models, runtime systems, and middleware support for many-core and/or heterogeneous computing platforms
– Tool support for performance optimization, debugging, and verification
– Generic and application-specific architectures such as reconfigurable systems in hardware and software
– Robust and fault-tolerant systems structures
– Architectures and design methods/tools for real-time embedded systems
– Cyber-physical systems and distributed computing architectures
– Organic and autonomic computing including both theoretical and practical results on self-organization, self-configuration, self-optimization, self-healing, and self-protection techniques
– Operating Systems, including but not limited to scheduling, memory management, power management, and real-time OS (RTOS) concepts
– Energy and power-aware computing, including green computing topics
– System aspects of ubiquitous and pervasive computing such as sensor nodes, novel input/output devices, novel computing platforms, architecture modeling, and middleware
– Architectures for robotics and automation systems
– Applications of embedded and cyber-physical systems
– High-performance and large scale parallel computing
– Approximate computing
– Post-Moore Architectures, including but not limited to quantum and neuromorphic computing

SUBMISSION GUIDELINES:
Submissions should be done through the link that is provided on the conference website. Papers must be submitted in PDF format. They should be formatted according to Springer LNCS style and must not exceed 12 pages, including references and figures.

The proceedings of ARCS 2017 will be published in the Springer Lecture Notes on Computer Science (LNCS) series. After the conference, it is planned that authors of selected papers will be invited to submit an extended version of their contribution for publication in a special issue of the Journal of Systems Architecture. Further, a best paper and best presentation award will be presented at the conference.

WORKSHOP AND TUTORIAL PROPOSALS:
Proposals for workshops and tutorials within the technical scope of the conference are solicited. Submissions should be done through email directly to the corresponding chair: Carsten Trinitis (Carsten.Trinitis@tum.de)

ORGANIZING COMMITTEE:
General Co-Chairs:
Jens Knoop, Vienna University of Technology, Austria
Wolfgang Karl, Karlsruhe Institute of Technology, Germany

Program Co-Chairs:
Martin Schulz, Lawrence Livermore National Laboratory, USA
Koji Inoue, Kyushu University, Japan

Workshop and Tutorial Co-Chairs:
Carsten Trinitis, Technische Universität München, Germany

Publicity Chair:
Miquel Pericàs, Chalmers University of Technology, Sweden

Publication Chair:
Thilo Piontek, Magdeburg University, Germany

Call for Papers: MULTIPROG 2017

The Tenth International Workshop on Programmability and Architectures for Heterogeneous Multicores (MULTIPROG-2016)
http://research.ac.upc.edu/multiprog/
in conjunction with HiPEAC
Stockholm, Sweden
January 24, 2017

IMPORTANT DATES:
Paper submission: October 21, 2016
Author notification: November 27, 2016

The ninth edition of the MULTIPROG workshop aims to bring together researchers interested in programming models, runtimes, and computer architecture. The workshop’s emphasis is on heterogeneous architectures and covers issues such as:
– How can future parallel programming models improve software productivity?
– How should compilers, runtimes and architectures support programming models and emerging applications?
– How to design efficient data structures and innovative algorithms?

MULTIPROG is intended for quick publication of early results, work-in-progress, etc., and is not intended to prevent later publication of extended papers. Informal proceedings with accepted papers will be made available at the workshop and online at the workshop’s web page.

Papers are sought on topics including, but not limited to:
1) Multi-core architectures
– Architectural support for compilers/programming models
– Processor (core) architecture and accelerators, in particular GPUs
– Memory system architecture
– Performance, power, temperature, and reliability issues
2) Heterogeneous computing
– Algorithms and data structures for heterogeneous systems
– Applications for heterogeneous computing and real-time graphics
3) Programming models for multi-core architectures
– Language extensions
– Run-time systems
– Compiler optimizations and techniques
4) Benchmarking of multi-/many-core architectures
– Tools for discovering and understanding parallelism
– Tools for understanding performance and debugging
– Case studies and performance evaluation

SUBMISSION GUIDELINES:
Submissions should not exceed 12 pages and should be formatted according to the LNCS format for CS Proceedings. This limit includes text, figures, tables and references. Please visit the workshop web site for detailed submission instructions.

ORGANIZERS:
Miquel Pericàs, Chalmers University of Technology
Vassilis Papaefstathiou, FORTH
Oscar Palomar, University of Manchester
Ferad Zyulkyarov, Barcelona Supercomputing Center

Program committee:
Abdelhalim Amer, Argonne National Lab
Ali Jannesari, UC Berkeley
Avi Mendelson, Technion
Chris Adeyeni-Jones, ARM
Christos Kotselidis, University of Manchester
Dong Ping Zhang, AMD
Håkan Grahn, Blekinge TH
Hans Vandierendonck, Queen’s University Belfast
Kenjiro Taura, University of Tokyo
Magnus Sjalander, NTNU
Oscar Plata, University of Malaga
Pedro Trancoso, University of Cyprus
Polyvios Pratikakis, FORTH-ICS
Roberto Gioiosa, PNNL
Sasa Tomic, IBM Research
Timothy G. Mattson, Intel
Trevor E. Carlson, Uppsala University
Yungang Bao, ICT-CAS

Call for Papers: ISCA 2017

The 44rd ACM/IEEE International Symposium on Computer Architecture (ISCA)
http://isca17.ece.utoronto.ca/doku.php
Toronto, Canada
June 25-28, 2017

IMPORTANT DATES
– Abstract Deadline: November 11, 2016, 11:59:59PM EST (Mandatory)
– Final Submission Deadline: November 18, 2016, 11:59:59PM EST no extensions
– Rebuttal Period: Early/mid February 2017
– Author Notification: March 8, 2017
– Final Manuscript Submission: May 1, 2017
– Early Registration Deadline: May 1, 2017

The International Symposium on Computer Architecture is the premier forum for new ideas and experimental results in computer architecture. The conference specifically seeks particularly forward-looking and novel submissions. Papers are solicited on a broad range of topics, including (but not limited to):
– Processor, memory, and storage systems architecture
– Parallel and multicore systems
– Data-center scale computing
– Architectures for handheld and mobile devices
– Application-specific, reconfigurable, or embedded architectures
– Accelerator-based architectures
– Architectures for security and virtualization
– Power and energy efficient architectures
– Interconnection networks
– Instruction, thread, and data-level parallelism
– Dependable architectures
– Architectural support for programming productivity
– Network processor and router architectures
– Architectures for emerging technologies and applications
– Effect of circuits and technology on architecture
– Architecture modeling and simulation methodology
– Performance evaluation and measurement of real systems

ORGANIZERS:
– General Chair: Andreas Moshovos, University of Toronto
– Program Chair: David Brooks, Harvard University
– Finance Chair: Mike Ferdman, University of New York, Stony Brook
– Tutorials Chair: Paul Gratz, Texas A&M
– Workshops Chair: TBD
– Publicity Chair: Christina Delimitrou, Cornell University
– Web and Social Media Chair: Gennady Pekhimenko, MSR and University of Toronto
– Publications Chair: Mahdi Bojnordi, University of Utah
– Student Travel Awards Chair: Natalie Enright Jerger, University of Toronto
– Registrations Chair: Adrian Sampson, Cornell University
– Industry Laison Chair: TBD

Program Committee:
TBA

Call for Nominations: Athena Lecturer Award

Athena Lecturer Award
http://awards.acm.org/athena/nominations.cfm

Nomination Deadline: November 30, 2016

The Athena Lecturer Award celebrates women researchers who have made fundamental contributions to Computer Science. To date, 11 awards have been given: http://awards.acm.org/athena/all.cfm

In the past, this award was an ACM-W award and SIG officers were responsible for nominating the candidates each year. This year, however, the Athena Lecture Award moves from being an ACM-W award to being an ACM award, operating under the guidelines and structure of other ACM Awards. The nomination deadline is now November 30 and nominations no longer come through the SIGS but come through the standard online nominating form for all ACM awards:
http://awards.acm.org/athena/nominations.cfm and https://campus.acm.org/public/awards/nomination.cfm

Call for Papers: Special Issue of IEEE Micro — Top Picks 2017

Special Issue of IEEE Micro: Micro’s Top Picks from the 2016 Computer Architecture Conferences
https://sites.google.com/site/ieeemicro/call-for-papers/top-picks-2017—call-for-papers
May/June 2017

IMPORTANT DATES:
Submission Deadline: September 19, 2016 (11:59:59 pm EDT)
Author Notification: December 20, 2016
Final Papers Due: January 23, 2017
Publication Date: May/June 2017

IEEE Micro will publish its yearly “Micro’s Top Picks from the Computer Architecture Conferences” as its May / June 2017 issue. This issue collects some of this year’s most significant research papers in computer architecture based on novelty and potential for long-term impact. Any computer architecture paper (not a combination of papers) published in the top conferences of 2016 (including MICRO-49) is eligible. The Top Picks committee will recognize those significant and insightful papers that have the potential to influence the work of computer architects for years to come.

SUBMISSION GUIDELINES:
To simplify reviewing, there is a mandatory format for submissions. The submission website allows uploading two documents per submission. Please upload the following two documents separately as a single submission:

1. A three-page, two-column document using 10-point type. The first two pages should summarize the paper. The third page should argue for the potential of the work to have long-term impact, clearly articulating why and how it will influence other researchers and/or industry. In the third page, please also include what the citation of your paper would be if it won the test of time award in 10 years.

2. The final version of the original conference paper.

Submissions that do not follow this format will not be reviewed. The first document should contain the names of the authors with a footnote that contains the title of the original conference paper, with the full name of the conference, page numbers, and date of publication.

ACCEPTED PAPER GUIDELINES:
Authors of accepted papers will receive further instructions on how to prepare the final papers to conform to IEEE Micro’s guidelines. Final papers should not exceed 5,000 words including references, with each average-size figure counting as 250 words toward this limit. Papers must have at least 30% new content compared to the original conference publication. Final papers will be edited for structure, style, clarity, and readability.

ORGANIZERS:
Special Issue Guest Editors (and Selection Committee Co-Chairs):
Aamer Jaleel, NVIDIA
Moinuddin Qureshi, Georgia Tech

Selection Committee:
TBD

Call for Participation: IISWC 2016

The 2016 IEEE International Symposium On Workload Characterization (IISWC)
http://www.iiswc.org
Providence, Rhode Island, USA
Sep 25-27, 2016

IMPORTANT DATES:
Early Registration Deadline: Sep 12, 2016
Hotel Reservation Deadline: Sep 12, 2016

IISWC provides a high-quality international forum to bring together researchers and practitioners from academia and industry to discuss cutting-edge research on understanding and characterization of workloads that run on all types of computing systems. Whether they are smart phones and deeply embedded systems at the low end or massively parallel systems at the high end, the design of future computing machines can be significantly improved if we understand the
characteristics of the workloads that are expected to run on them.

IISWC registration site: https://www.regonline.com/Register/Checkin.aspx?EventID=1855835

Keynote speakers:
Ravi Iyer, Intel
Alanson Sample, Disney Research

The conference program is available online at http://www.iiswc.org/iiswc2016/program2016.html

IISWC is sponsored by IEEE Computer Society and the Technical Committee on Computer Architecture.

Call for Submissions: Workshop on Accelerator Programming using Directives

Third Workshop on Accelerator Programming using Directives (WACCPD)
http://waccpd.org/
co-located with SC’16
Salt Lake City, Utah, USA
November 14, 2016

IMPORTANT DEADLINES
Submission Deadline: September 9, 2016 (firm deadline)
Author notification: October 7, 2016
Camera Ready papers due: October 13, 2016

One of the hard realities is that the hardware continues to evolve very rapidly with diverse memory subsystems or cores with different ISAs or accelerators of varied types. The HPC community is in constant need for sophisticated software tools and techniques to port legacy code to these emerging platforms. Maintaining a single code base yet achieving performance portable solution continues to pose a daunting task. Directive-based programming models such as OpenACC, OpenMP tackle this issue by offering scientists a high-level approach to accelerate scientific applications and develop performance portable solutions. This enables accelerators to be first-class citizens for HPC!

This workshop aims to solicit papers that explore innovative language features – their implementations, compilation & runtime scheduling techniques, performance optimization strategies, auto-tuning tools exploring the optimization space and so on.

Topics of interest for workshop submissions include, but are not limited to:
– Compiler and Runtime support for current and emerging architectures
– Language-based extensions
– Memory management using directives
– Performance evaluation and lessons learnt
– Auto-tuning and optimization strategies
– Programming experience porting applications in any domain
– Extensions to and shortcomings of current accelerator directives APIs
– Hybrid heterogeneous or many-core programming with accelerator directives with other models (i.e. OpenMP, MPI, OpenSHMEM)
– Scientific libraries interoperability with accelerator directives
– Experiences in implementing compilers for accelerator directives on newer architectures
– Low level communication APIs or runtimes that support accelerator directives
– Asynchronous execution and scheduling (heterogeneous tasks)
– Power / energy studies
– Modeling and performance analysis tools
– Benchmarks and validation suites

BEST PAPER AWARD:
NVIDIA has generously offered to sponsor the ‘Best Paper Award’ with NVIDIA’s newest Pascal compute capable card. This award will be given to the author(s) of the paper selected by the Technical Program Committee and the Program Chairs. The award will be determined from viewpoints of the technical and scientific merits, impact on the science and engineering of the research work and the clarity of presentation of the research contents in the paper.

SUBMISSION GUIDELINES:
Submissions are limited to 10 pages. The 10-page limit includes figures, tables, and appendices, but does not include references, for which there is no page limit. Submissions must follow the ACM format. Submission site: https://easychair.org/conferences/?conf=waccpd2016

Submitted papers should not have appeared in or be under consideration for a different workshop, conference or journal. It is also expected that all accepted papers will be presented at the workshop by one of the authors.

ORGANIZERS:
Guido Juckeland, Helmholtz-Zentrum Dresden-Rossendorf, Dresden, Germany
Sunita Chandrasekaran, University of Delaware, Newark, DE, USA

STEERING COMMITTEE:
Barbara Chapman (StonyBrook University, cOMPunity, USA)
Oscar Hernandez (ORNL, USA)
Kuan-Ching Li (Providence University, Taiwan)
Satoshi Matsuoka (Titech, Japan)
Duncan Poole (OpenACC)
Thomas Schulthess (ORNL, USA)
Jeff Vetter (ORNL, USA)

PROGRAM COMMITTEE:
Christopher Bergstorm (Pathscale)
James Beyer (NVIDIA, USA)
Henri Callandra (TOTAL, USA)
Robert Dietrich (TU Dresden, Germany)
Fernanda Foertter (ORNL, USA)
Mark Govette (NOAA, USA)
Georg Hager (FAU, Germany)
Jeff Hammond (Intel, USA)
Christian Iwainsky (TU Darmstadt, Germany)
Arpith J. Jacob (IBM, USA)
Henri Jin (NASA-Ames, USA)
Adrian Jackson (EPCC, UK)
Wayne Joubert (ORNL, USA)
Michael Klemm (Intel, Germany)
Seyong Lee (ORNL, USA)
CJ Newburn (NVIDIA, USA)
Antonio J. Pena (BSC, Spain)
William Sawyer (CSCS, Switzerland)
Thomas Schwinge (MentorGraphics, Germany)
Ray Sheppard (Indiana University, USA)
Peter Steinbach (Scionics, Germany)
Christian Terboven (RWTH Aachen University, Germany)
Cheng Wang (Microsoft, USA)
Michael Wolfe (NVIDIA, USA)

Call for Workshops and Tutorials: HPCA 2017

International Symposium on High-Performance Computer Architecture (HPCA)
http://hpca2017.org
Austin, Texas, USA
February 4-8, 2017

IMPORTANT DATES:
– Deadline for submission: September 16, 2016, 11:59 PM EDT
– Notification of acceptance: October 10, 2016

The 2017 IEEE International Symposium on High-Performance Computer Architecture (HPCA-23) is seeking proposals for workshops and tutorials to accompany the conference. Workshops and tutorials will be held on Saturday-Sunday, February 4-5, and may be a half day or a full day in length.

We encourage members of the community to consider submitting proposals for workshops and tutorials that bring together researchers and practitioners working on research topics of significant current interest to the HPCA community.
Prospective workshop and tutorial organizers are invited to submit proposals by completing the online submission form: https://goo.gl/forms/gtVJovHbb5PbfHE32

For questions, please contact the Workshops and Tutorials chair, Michael Ferdman (mferdman@cs.stonybrook.edu).