Call for Papers:

DATE 2021: Dependability and System-level Test

Abstract or Paper Registration Deadline
September 14, 2020
Final Submission Deadline
September 21, 2020

Topic T3: Dependability and System-level Test
Test and Dependability Track @ DATE 2021
Grenoble, France
February 1-5, 2021

Submissions Due: September 21, 2020

DEADLINES: The deadline to submit papers is 
Abstract: Sunday, September 14, 2020 23:59:59 CET.

For a paper to be considered a valid submission, at least a title, abstract, and the complete list of authors (cannot be modified after Monday, September 14, 2020 23:59:59 CET) should be submitted by this date. The full paper can be submitted at the same time or later, but must be uploaded at the latest by

Full Paper: Monday, September 21, 2020 23:59:59 CET.

Please note that there will not be any additional deadline extensions beyond Monday, September 21, 2020 23:59:59 CET.

DATE 2021
The 24th DATE conference and exhibition is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in the hardware and software design, test and manufacturing of electronic circuits and systems. DATE puts strong emphasis on both technology and systems, covering ICs/SoCs, reconfigurable hardware and embedded systems, and embedded software. The conference addresses all aspects of research into technologies for electronic and (embedded) systems engineering. It covers the design process, test, and tools for design automation of electronic products ranging from integrated circuits to distributed large-scale systems. This includes both hardware and embedded software design issues. The conference scope also includes the elaboration of design requirements and new architectures for challenging application fields such as telecom, wireless communications, multimedia, healthcare and automotive systems.

Persons involved in innovative industrial designs are particularly encouraged to submit papers to foster the feedback from design to research. Panels, hot-topic sessions and embedded tutorials highlight and inform about emerging topics. The Test and Dependability track addresses various quality aspects of electronic and embedded systems. The emphasis is on test technology, design-for-testability, security, reliability and other dimensions of dependability. The track’s focus includes significant improvements on existing methods, algorithms and tools as well as forward-looking approaches related to these topics.

The Dependability and System-level Test topic is one of the six topics foreseen in the Test and Dependability track. It is devoted to the presentation and discussion of state-of-the-art advances in the theory and practice of hardware and software solutions for system’s dependability crossing all layers of the system’s stack. Topics of interest include, but are not limited to:

  • microarchitecture-level and system-level error/fault modeling; 
  • cross-layer dependability analysis and evaluation; 
  • reliable and fail-safe architectures and systems design; 
  • system-level on-line test and functional safety; 
  • runtime system management for dependability; 
  • cross-layer solutions for dependability (microarchitecture-level, software-level, system-level); 
  • application resilience; 
  • high-level synthesis (HLS) dependability;
  • approximate computing for resilient systems;
  • computational intelligence methods (AI/ML) for dependability; 
  • system-level and microarchitecture-level solutions for safety- and mission-critical systems, IoT and cloud infrastructure

Karthik Pattabiraman, University of British Columbia (chair)
Stefano Di Carlo, Politecnico di Torino (cp-chair),
Jyotika Athavale, Intel Corp
Görschwin Fey, Hamburg University of Technology
Dimitris Gizopoulos, University of Athens
Paolo Rech, UFRGS
Juan Carlos Ruiz Garcia, UPV Valencia
Rishad Shafik, Newcastle University

Submission instructions can be found on the conference web page: