Archive of Announcements


Announcements of book and tool releases, calls for award nominations, SIGARCH-focused announcements. Ordered by date posted on this website.


Book Release: On-Chip Networks, 2nd edition

On-Chip Networks, Second Edition (Jerger/Krishna/Peh): This book targets engineers and researchers familiar with basic computer architecture concepts who are interested in learning about on-chip networks. This work is designed to be a short synthesis of the most critical concepts in on-chip network design. It is a resource for both understanding on-chip network basics and for providing an overview of state-of-the-art research in on-chip networks. We believe that an overview that teaches both fundamental concepts and highlights state-of-the-art designs will be of great value to both graduate students and industry engineers. While not an exhaustive text, we hope to illuminate fundamental concepts for the reader as well as identify trends and gaps in on chip network research.

Call for Nominations: MICRO Test of Time Award 2017

The MICRO Test of Time (ToT) Award Committee is soliciting nominations for the third MICRO ToT Award to be given at the International Symposium on Microarchitecture in October 2017, to be held in Boston, MA, USA. This recognizes the most influential papers published in past MICRO conferences that have had significant impact in the field.

Book Release: Space-Time Computing with Temporal Neural Networks

Understanding and implementing the brain’s computational paradigm is the one true grand challenge facing computer researchers. Not only are the brain’s computational capabilities far beyond those of conventional computers, its energy efficiency is truly remarkable. This book, written from the perspective of a computer designer and targeted at computer researchers, is intended to give both background and lay out a course of action for studying the brain’s computational paradigm. It contains a mix of concepts and ideas drawn from computational neuroscience, combined with those of the author. As background, relevant biological features are described in terms of their computational and communication properties. The brain’s neocortex is constructed of massively interconnected neurons that compute and communicate via voltage spikes, and a strong argument can be made that precise spike timing is an essential element of the paradigm Drawing from the biological features, a mathematics-based computational paradigm is constructed. The key feature is spiking neurons that perform communication and processing in space-time, with emphasis on time. In these paradigms, time is used as a freely available resource for both communication and computation. Neuron models are first discussed in general, and one is chosen for detailed development. Using the model, single-neuron computation is first explored. Neuron inputs are encoded as spike patterns, and the neuron is trained to identify input pattern similarities. Individual neurons are building blocks for constructing larger ensembles, referred to as “columns”. These columns are trained in an unsupervised manner and operate collectively to perform the basic cognitive function of pattern clustering. Similar input patterns are mapped to a much smaller set of similar output patterns, thereby dividing the input patterns into identifiable clusters. Larger cognitive systems are formed by combining columns into a hierarchical architecture. These higher level architectures are the subject of ongoing study, and progress to date is described in detail in later chapters. Simulation plays a major role in model development, and the simulation infrastructure developed by the author is described.

Call for Student Travel Grant Applications: ISCA 2017

DEADLINE: Travel grant application form must be received by 11:59pm EDT, May 8, 2017 With generous support from the U.S. National Science Foundation, ACM SIGARCH, and IEEE TC on Computer Architecture, ISCA-44 will offer travel grants for students to deDetails…

WHISPER: A New Persistent Memory Benchmark Suite

To put future research in Persistent Memory software and hardware on a firmer footing, researchers from Wisconsin and HP Labs have developed a PM benchmark suite called WHISPER whose open source is available now. They took benchmarks that used PM directly (echo, n-store), via libraries (reds, c-tree, hashmap, vacation, memcached) and as a file system (nfs, exim, mysql) and modified them so that accesses use volatile memory except as necessary to provide consistent state for crash recovery.

Call for Nominations: The 2017 IEEE TCCA Young Computer Architect Award

The IEEE TCCA Young Computer Architect Award recognizes outstanding research contributions by an individual in the field of Computer Architecture, who received his/her PhD degree within the last 6 years. The Award will be presented at the Awards Banquet at the 2017 International Symposium on Computer Architecture (ISCA). The IEEE Computer Society administers the award.

Call for Nominations: ACM SIGARCH Student Scholarships for ACM’s Celebration of 50 Years of the ACM Turing Award

ACM SIGARCH has a limited number of scholarships to award to worthy students to attend the Celebration of 50 Years of the ACM Turing Award 23-24 June 2017 at the Westin St. Francis in San Francisco, CA. Each scholarship includes 2 nights at the Westin St. Francis Hotel in San Francisco and up to $900 to help offset the cost of travel and subsistence (Students will receive a check from ACM upon submission of receipts for travel).

SIGARCH statement on the US travel ban

SIGARCH expresses concerns about the presidential executive order restricting entry into the USA.