Archive of Announcements
Announcements of book and tool releases, calls for award nominations, SIGARCH-focused announcements. Ordered by date posted on this website.
Computer Architecture Podcasts: a series of conversations on cutting-edge work in computer architecture and the remarkable people behind it. Announcing the release of Episode 2: Domain-specific Accelerators with Dr. Bill Dally, the Chief Scientist andDetails…
The MICRO Test of Time (ToT) Award Committee is soliciting nominations for the seventh MICRO ToT Award. This award recognizes the most influential papers published in past MICRO conferences that have had significant impact in the field. Visit https://www.microarch.org/tot/cfn.html for information on the nomination process.
The goal of the workshop is to provide an avenue for undergraduate and early Master’s students to explore Computer Architecture. We are bringing together undergraduate students from the more than 20 countries, especially from the EMEA region, ranging from Ghana to Bosnia to Scotland to attend uArch workshop and MICRO.
Eurosys is organizing a shadow program committee for the EuroSys 2021 conference under the sponsorship of EuroSys. If you are interested in participating, please apply online at https://eurosys21shadowpc-apps.hotcrp.com/ before September 18, 2020.
Morgan & Claypool is proud to announce a recently published book in our Computer Architecture series. Data Orchestration in Deep Learning Accelerators
2nd edition of “A Primer on Memory Consistency and Cache Coherence” now Open Access.
The MICRO 2020 symposium will be held as a global online event, to allow everyone from around the world to participate and enjoy the experience. Details about the technical program and the registration and participation procedures will be announced during the coming weeks. The committees of MICRO 2020 wish you are all staying well and safe.
Morgan & Claypool is proud to announce a recently published book in our Computer Architecture series. Quantum Computer Systems Research for Noisy Intermediate-Scale Quantum Computers Yongshan Ding, University of Chicago Frederic T. Chong, UniversitDetails…
Morgan & Claypool is proud to announce a recently published book in our Computer Architecture series. Efficient Processing of Deep Neural Networks Vivienne Sze, Massachusetts Institute of Technology Yu-Hsin Chen, Massachusetts Institute of TechnoloDetails…
SIGARCH, SIGMICRO, TCCA and TCuARCH join together to express our denunciation of racism and to stand together, particularly in support of African American members of our community, as representatives of our research community. Together, we mourn the innocent Black lives violently taken recently, without cause, including but not limited to George Floyd, Breonna Taylor and Ahmaud Arbery.
ACM and IEEE have empaneled a Joint Investigative Committee (JIC) to investigate claims of potential breaches to the peer review process of the 2019 ISCA conference. The JIC consists of senior ACM and IEEE volunteers who are not directly related to the Computer Architecture community. A professional legal team and investigators are supporting them. The JIC is also cooperating with multiple, parallel related investigations by other organizations.
Introducing the Computer Architecture Podcasts: a series of conversations on cutting-edge work in computer architecture and the remarkable people behind it. Listen to the first episode with Dr. Kim Hazelwood from Facebook on Systems for ML and having aDetails…
We are looking forward to welcoming you to the first-ever virtual ISCA! We believe the ecosystem we have put together will allow you to get the maximum out of this worldwide event.
“Happy Hour with Architects” is a Zoom session on different topics related to computer architecture. It is a platform to discuss and debate various topics and does not only focus on technical content. The sessions are all recorded and made available on YouTube.
ACM SIGARCH Alan D. Berenbaum Distinguished Service Award Nominations deadline extended to May 15, 2020. This annual award is presented to an individual who has contributed important service to the computer architecture community.
Morgan & Claypool is proud to announce a recently published book in our Computer Architecture series. A Primer on Memory Consistency and Cache Coherence, Second Edition
The JIC was established by ACM and IEEE to investigate alleged policy violations in connection with the ISCA and HPCA conferences in 2019. I am writing to provide you with several important updates.
Today we release the second version of QFlex (v2.0) which includes the trace, timing, and FPGA-accelerated simulation modes.
It is my great pleasure to announce that ASPLOS 2020 is open and to welcome everyone, virtually of course, to Lausanne Switerland! The papers and talk videos are online, and the Slack workspace is ready to host lively discussions.
The MICRO-53 committees recognize the difficulties that the COVID-19 pandemic puts on everyone’s shoulders around the globe. As a response to these difficulties and as an effort to relieve the stress on all authors, MICRO is extending the paper submission deadlines and corresponding timeline.
Given the recent uncertainty and increasing travel restrictions related to COVID-19, the ISPASS 2020 Organizing Committee has been discussing with both the ISPASS Steering Committee and IEEE Computer Society regarding options for ISPASS 2020. We just received confirmation that the meeting will be rescheduled during the period August 22-26, 2020. We will be providing additional information on the rescheduled meeting soon. We were able to confirm the same hotel in August.
Morgan & Claypool Publishers is proud to announce the recent publication of: A Primer on Memory Consistency and Cache Coherence, Second Edition
Established in memory of Dr. B. (Bob) Ramakrishna Rau, this award recognizes his distinguished career in promoting and expanding the use of innovative computer microarchitecture techniques, including his innovation in compiler technology, his leadership in academic and industrial computer architecture, and his extremely high personal and ethical standards.
The Vienna Center for Logic and Algorithms of TU Wien (Vienna University of Technology), calls for the nomination of authors of outstanding theses and scientific works in the field of Logic and Computer Science, onferred between 15.11.2018 and 31.12.2019 (inclusive). Deadline: 25.3.2020
We recently communicated an announcement about an ACM SIGARCH / IEEE TCCA jointly-appointed committee investigating the review process related to an accepted ISCA’19 paper. In this announcement, we would like to provide further information about how the investigation was conducted.
The February 1 deadline for nominating a 2019 PhD dissertation to the SIGARCH/TCCA Outstanding Dissertation Award is fast approaching. Nominated dissertations must have been defended and deposited in 2019.
The term of the current Editor-in-Chief (EiC) of the ACM Transactions on Architecture and Code Optimization (TACO) is coming to an end, and the ACM Publications Board has set up a nominating committee to assist the Board in selecting the next EiC.
The HPCA Test of Time (ToT) Award Committee is soliciting nominations for the second HPCA ToT Award to be given at the International Symposium on High Performance Computer Architecture in February 2020, to be held in San Diego, CA. This award recognizes the most influential papers published in past HPCA conferences that have had significant impact in the field.
Computer Architecture Letters (CAL) recently began soliciting short “lightning talk” videos from authors of accepted papers. https://www.youtube.com/playlist?list=PLsSbdutlPKONPqyURlIlQYJfXabbedngM
Looking for more artifact evaluators for ASPLOS’20
The jointly appointed committee of the IEEE Computer Society TCCA and ACM SIGARCH has concluded its investigation into the peer-review process of ISCA 2019.
We are holding the third Chisel Community Conference, located at Western Digital’s Milpitas campus, on January 29-30, 2020 (more details forthcoming). Chisel is a hardware-construction language, hosted in Scala, and is used in both academia and industry to generate RTL for digital hardware. This will be the third event promoting the Chisel language, FIRRTL compiler, and associated software ecosystem, bringing together the community for multiple talks, tutorials, workshops and more.
The memory system has the potential to be a hub for future innovation. While conventional memory systems focused primarily on high density, other memory system metrics like energy, security, and reliability are grabbing modern research headlines. With processor performance stagnating, it is also time to consider new programming models that move some application computations into the memory system. This, in turn, will lead to feature-rich memory systems with new interfaces. The past decade has seen a number of memory system innovations that point to this future where the memory system will be much more than dense rows of unintelligent bits. This book takes a tour through recent and prominent research works, touching upon new DRAM chip designs and technologies, near data processing approaches, new memory channel architectures, techniques to tolerate the overheads of refresh and fault tolerance, security attacks and mitigations, and memory scheduling.
The recent publications from IEEE Computer Architecture Letters (CAL).
AMD Research would like to invite under-represented minorities – for example, but not limited to, gender, ethnic, racial, LGBTQIA – of the MICRO community to join us for a dessert social celebrating diversity and inclusion at MICRO-52.
There are members of the community who have come forward with allegations of ethics violations (e.g., including personal or email contacts requesting support for a paper under review). We ask members of our community with any knowledge of behavior that violates these codes to come forward, by contacting “firstname.lastname@example.org”.
In light of the recent tragedy of a PhD student’s death, we hereby inform the community that there is an ongoing investigation into the alleged reviewing irregularities surrounding the event. The investigation was launched by IEEE TCCA and ACM SIGARCH, in cooperation with IEEE and ACM.
The MICRO Test of Time (ToT) Award Committee is soliciting nominations for the fifth MICRO ToT Award to be given at the International Symposium on Microarchitecture in October 2019, to be held in Columbus, Ohio. This award recognizes the most influential papers published in past MICRO conferences that have had significant impact in the field.
The IEEE Computer Architecture Letters (CAL) Editorial Board is pleased to highlight the recent publication of the following letters: Modeling Emerging Memory-Divergent GPU Applications by Lu Wang, Magnus Jahre, Almutaz Adileh, Zhiying Wang, Lieven EecDetails…
This book summarizes the landscape of cache replacement policies for CPU data caches. The emphasis is on algorithmic issues, so the authors start by defining a taxonomy that places previous policies into two broad categories, which they refer to as coarse-grained and fine-grained policies. Each of these categories is then divided into three subcategories that describe different approaches to solving the cache replacement problem, along with summaries of significant work in each category.
Dear members of the computer architecture community, The ACM SIGARCH and IEEE TCCA Executive Committees, and the ISCA Steering Committee express their deepest condolences to the family, friends, and colleagues of Huixiang Chen, a doctoral student at thDetails…
The aim of this book is to introduce the big picture of heterogeneous computing. Whether you are a hardware designer or a software developer, you need to know how the pieces of the puzzle fit together. The main goal is to bring researchers and engineers to the forefront of the research frontier in the new era that started a few years ago and is expected to continue for decades. We believe that academics, researchers, practitioners, and students will benefit from this book and will be prepared to tackle the big wave of heterogeneous computing that is here to stay.
We are looking for a General Chair (GC) and a location to host ISCA 2021.
WICARCH has launched a new monthly webinar series. Recordings of our webinars can be found on our YouTube channel: https://www.youtube.com/channel/UC-ZzTR5GIrGSty5aG0su6qg.
Honoring contributions to the computer microarchitecture field. Submit your nomination by 1 May 2019.
This book presents the principles for design of new secure processor architectures.
Call for Nominations: ACM/IEEE CS Eckert-Mauchly Award by 30 March
ACM SIGARCH Alan D. Berenbaum Distinguished Service Award This annual award is presented to an individual who has contributed important service to the computer architecture community. The award is presented annually at the International Symposium on CoDetails…
ACM SIGARCH Maurice Wilkes Award The award of $2,500 is given annually for an outstanding contribution to computer architecture made by an individual whose computer-related professional career (graduate school or full-time employment, whichever began fDetails…
The IEEE TCCA Young Computer Architect Award recognizes outstanding research contributions by an individual in the field of Computer Architecture, who received his/her PhD degree within the last 6 years. The Award will be presented at the Awards BanqueDetails…
2019 ACM SIGARCH/IEEE CS TCCA Outstanding Dissertation Award Call for Nominations ELIGIBILITY: Eligible dissertations must have been successfully defended and deposited in the previous calendar year. Each nominated dissertation must be on a topic relevDetails…
The SIGARCH 2019 elections nominating committee is delighted to announce the following slate of candidates for the upcoming SIGARCH elections. Chair: Babak Falsafi Gabe Loh Vice-chair: Natalie Enright Jerger Mattan Erez Treasurer: Rajeev BalasubramoniaDetails…
Report on the NSF-Sponsored Community Visioning Workshop on “Inter-Disciplinary Research Challenges in Computer Systems for the 2020s”
The final report on the NSF-Sponsored Community Visioning Workshop on “Inter-Disciplinary Research Challenges in Computer Systems for the 2020s” is now available. It is downloadable from the ACM Digital Library in https://dl.acm.org/citation.cfm?id=3297279&picked=prox The report summarizes the findings of the workshop, which was held in Williamsburg, VA, in March 2018 (https://www.asplos2018.org/grandchallenges/). Please kindly distribute it to your colleagues. We also appreciate feedback, which can be sent to email@example.com. Albert Cohen, Xipeng Shen, Josep Torrellas, James Tuck, and Yuanyuan Zhou
Call for Nominations for SIGARCH Executive Committee Elections The SIGARCH elections nominating committee invites nominations (including self-nominations) for candidates to serve on the SIGARCH Executive Committee (EC). The nominating committee will seDetails…
We would like to introduce to the community our new and improved Automata processing benchmark suite, AutomataZoo [Wadden et al., IISWC 2018].
Please nominate work eligible for the HPCA Test of Time Award – Deadline 12/1/2019.
This book describes warehouse-scale computers (WSCs), the computing platforms that power cloud computing and all the great web services we use every day. It discusses how these new systems treat the datacenter itself as one massive computer designed at warehouse scale, with hardware and software working in concert to deliver good levels of internet service performance. The book details the architecture of WSCs and covers the main factors influencing their design, operation, and cost structure, and the characteristics of their software base. Each chapter contains multiple real-world examples, including detailed case studies and previously unpublished details of the infrastructure used to power Google’s online services. Targeted at the architects and programmers of today’s WSCs, this book provides a great foundation for those looking to innovate in this fascinating and important area, but the material will also be broadly interesting to those who just want to understand the infrastructure powering the internet.
With growing interest in computer security and the protection of the code and data which execute on commodity computers, the amount of hardware security features in today’s processors has increased significantly over the recent years. No longer of just academic interest, security features inside processors have been embraced by industry as well, with a number of commercial secure processor architectures available today. This book aims to give readers insights into the principles behind the design of academic and commercial secure processor architectures. Secure processor architecture research is concerned with exploring and designing hardware features inside computer processors, features which can help protect confidentiality and integrity of the code and data executing on the processor. Unlike traditional processor architecture research that focuses on performance, efficiency, and energy as the first-order design objectives, secure processor architecture design has security as the first-order design objective (while still keeping the others as important design aspects that need to be considered).
Persistent Impact Prize for Non-Volatile Memory Research Nominations due: December 1, 2019, midnight AoE. The Non-Volatile Memories Workshop (NVMW) Organizing Committee requests nominations for the 2019 Persistent Impact Prize. The prize is awarded annDetails…
SIGARCH is happy to announce that iscaconf.org is now live. The web site will serve as a permanent repository for all former ISCA web sites as well as a hosting platform for the future ones. Some of the former ISCA sites are no longer online. If you weDetails…
Announcing the Versatile Tensor Accelerator (VTA) is an extension of the TVM framework designed to advance deep learning and hardware innovation.
The MICRO Test of Time (ToT) Award Committee is soliciting nominations for the fifth MICRO ToT Award. This award recognizes the most influential papers published in past MICRO conferences that have had significant impact in the field. This year, the award will recognize an influential MICRO paper published between 1996 and 2000 (inclusive). Nominations are due by July 31, 2018 (see https://www.microarch.org/Micro-ToT-Award/cfn.html for details on how to nominate a paper).
The Women in Computer Architecture (WICARCH) organizing committee is conducting a survey to broadly assess the climate in computer architecture and more specifically how WICARCH initiatives are being received. We hope you will take 10 minutes to fill oDetails…
Originally developed to support video games, graphics processor units (GPUs) are now increasingly used for general-purpose (non-graphics) applications ranging from machine learning to mining of cryptographic currencies. GPUs can achieve improved performance and efficiency versus central processing units (CPUs) by dedicating a larger fraction of hardware resources to computation. In addition, their general-purpose programmability makes contemporary GPUs appealing to software developers in comparison to domain-specific accelerators. This book provides an introduction to those interested in studying the architecture of GPUs that support general-purpose computing. It collects together information currently only found among a wide range of disparate sources. The authors led development of the GPGPU-Sim simulator widely used in academic research on GPU architectures.
Visioning Workshops in Computer Architecture Next proposal deadline: September 3, 2018 The ACM Special Interest Group in Computer Architecture (SIGARCH) invites proposals for visioning workshops that will catalyze and enable innovative research withinDetails…
The MLPerf benchmark suite aims to provide a consistent way to measure the performance of machine learning hardware platforms, software frameworks, and cloud services.
2019 IEEE-CS Charles Babbage Award Deadline: October 1, 2018 Nomination site: awards.computer.org ABOUT THE IEEE-CS CHARLES BABBAGE AWARD: Established in memory of Charles Babbage in recognition of significant contributions in the field of parallel comDetails…
Established in memory of Dr. B. (Bob) Ramakrishna Rau, the Rau award recognizes his distinguished career in promoting and expanding the use of innovative computer microarchitecture techniques, including his innovation in compiler technology, his leadership in academic and industrial computer architecture, and his extremely high personal and ethical standards.
Call for Nominations: for the 2018 IEEE TCCA Young Computer Architect Award
2018 ACM/IEEE-CS Eckert-Mauchly Award Submission deadline: March 30, 2018 ACM and the IEEE Computer Society co-sponsor the Eckert-Mauchly Award, which was initiated in 1979. The award is known as the computer architecture community’s most prestigious aDetails…
IEEE Micro Seeks Editor-in-Chief for 2019-2021 Term Application deadline: March 30, 2018 IEEE Micro, a bimonthly publication of the IEEE Computer Society, reaches an international audience of microcomputer and microprocessor designers, system integratoDetails…
Most emerging applications in imaging and machine learning must perform immense amounts of computation while holding to strict limits on energy and power. To meet these goals, architects are building increasingly specialized compute engines tailored for these specific tasks. The resulting computer systems are heterogeneous, containing multiple processing cores with wildly different execution models. Unfortunately, the cost of producing this specialized hardware—and the software to control it—is astronomical. Moreover, the task of porting algorithms to these heterogeneous machines typically requires that the algorithm be partitioned across the machine and rewritten for each specific architecture, which is time consuming and prone to error. Over the last several years, the authors have approached this problem using domain-specific languages (DSLs): high-level programming languages customized for specific domains, such as database manipulation, machine learning, or image processing. By giving up generality, these languages are able to provide high-level abstractions to the developer while producing high-performance output. The purpose of this book is to spur the adoption and the creation of domain-specific languages, especially for the task of creating hardware designs.
ACM SIGARCH Maurice Wilkes Award Nominations Deadline: March 15, 2018 The award of $2,500 is given annually for an outstanding contribution to computer architecture made by an individual whose computer-related professional career (graduate school or fuDetails…
2018 ACM SIGARCH/IEEE CS TCCA Outstanding Dissertation Award Nominations Deadline: February 15, 2018 The SIGARCH/TCCA Outstanding Dissertation award recognizes excellent thesis research by doctoral candidates in the field of computer architecture. DissDetails…
The IEEE TCCA Young Computer Architect Award recognizes outstanding research contributions by an individual in the field of Computer Architecture, who received his/her PhD degree within the last 6 years.
Grad Cohort event San Francisco, USA April 13-14, 2018 Application deadline: January 20, 2018 Since 2004, CRA-W (Computing Research Association Committee on Women) has been running the very successful Grad Cohort program. Focused on graduate students,Details…
The 6th edition of Hennessy and Patterson is now available
The 1st edition of the RISC-V Reader by David Patterson and Andrew Waterman is available.
A large trace of the Microsoft Azure workload is now available in GitHub.
The Persistent Impact Prize (presented this year by Toshiba) will recognize outstanding research on non-volatile memories published at least five years ago.
Morgan & Claypool Publishers is proud to announce the publication of the first technical book on autonomous vehicles for a general computer science audience. Creating Autonomous Vehicle Systems is written by four leading research and development experts in the field and provides both underlying theory and practical applications for this fast-growing technology area. http://www.morganclaypoolpublishers.com/catalog_Orig/product_info.php?products_id=1090 This book will be useful to hardware and software engineers, students, and autonomous vehicle researchers and practitioners. Students interested in autonomous driving will find this a comprehensive overview of the entire autonomous vehicle technology stack. Researchers will find plenty of references for an effective, deeper exploration of the various technologies, and practitioners will find many practical techniques used successfully by the authors. Autonomous driving is not one single technology; it is an integration of many technologies. It demands innovations in algorithms, system integrations, and cloud platforms. Creating Autonomous Vehicle Systems covers each of these subsystems in detail: algorithms for localization, perception, and planning and control; client systems, such as the robotics operating system and hardware platform; and the cloud platform, which includes data storage, simulation, high-definition (HD) mapping, and deep learning model training. Review copies (eBook) are available for academic and professional courses as well as for media. Please contact Brent Beckley (firstname.lastname@example.org)
WICARCH (Women in Computer Architecture) are looking for more ways to engage our members. Please follow us on Facebook (https://www.facebook.com/wicarch/) and twitter (https://twitter.com/WICARCH).
The IEEE Technical Committee on Computer Architecture has a new website and re-booted mailing list! All SIGARCH members are invited to subscribe to the mailing list: http://ieeetcca.org/subscription/
This book provides computer engineers, academic researchers, new graduate students, and seasoned practitioners an end-to-end overview of virtual memory. We begin with a recap of foundational concepts and discuss not only state-of-the-art virtual memory hardware and software support available today, but also emerging research trends in this space. The span of topics covers processor microarchitecture, memory systems, operating system design, and memory allocation. We show how efficient virtual memory implementations hinge on careful hardware and software cooperation, and we discuss new research directions aimed at addressing emerging problems in this space. Virtual memory is a classic computer science abstraction and one of the pillars of the computing revolution. It has long enabled hardware flexibility, software portability, and overall better security, to name just a few of its powerful benefits. Nearly all user-level programs today take for granted that they will have been freed from the burden of physical memory management by the hardware, the operating system, device drivers, and system libraries. However, despite its ubiquity in systems ranging from warehouse-scale datacenters to embedded Internet of Things (IoT) devices, the overheads of virtual memory are becoming a critical performance bottleneck today. Virtual memory architectures designed for individual CPUs or even individual cores are in many cases struggling to scale up and scale out to today’s systems which now increasingly include exotic hardware accelerators (such as GPUs, FPGAs, or DSPs) and emerging memory technologies (such as non-volatile memory), and which run increasingly intensive workloads (such as virtualized and/or “big data” applications). As such, many of the fundamental abstractions and implementation approaches for virtual memory are being augmented, extended, or entirely rebuilt in order to ensure that virtual memory remains viable and performant in the years to come.
Machine learning, and specifically deep learning, has been hugely disruptive in many fields of computer science. The success of deep learning techniques in solving notoriously difficult classification and regression problems has resulted in their rapid adoption in solving real-world problems. The emergence of deep learning is widely attributed to a virtuous cycle whereby fundamental advancements in training deeper models were enabled by the availability of massive datasets and high-performance computer hardware. This text serves as a primer for computer architects in a new and rapidly evolving field. We review how machine learning has evolved since its inception in the 1960s and track the key developments leading up to the emergence of the powerful deep learning techniques that emerged in the last decade. Next we review representative workloads, including the most commonly used datasets and seminal networks across a variety of domains. In addition to discussing the workloads themselves, we also detail the most popular deep learning tools and show how aspiring practitioners can use the tools with the workloads to characterize and optimize DNNs. The remainder of the book is dedicated to the design and optimization of hardware and architectures for machine learning. As high-performance hardware was so instrumental in the success of machine learning becoming a practical solution, this chapter recounts a variety of optimizations proposed recently to further improve future designs. Finally, we present a review of recent research published in the area as well as a taxonomy to help readers understand how various contributions fall in context.
The HPCA Test of Time (ToT) Award Committee is soliciting nominations (due Oct 15, 2017) for the first HPCA ToT Award to be given at the International Symposium on High Performance Computer Architecture in February 2018, to be held in Vienna, Austria. This award recognizes the most influential papers published in past HPCA conferences that have had significant impact in the field.
Please join the new WICARCH listserv. Steps to enrolment: Join SIGARCH/SIGMICRO, specify gender as female in myACM profile, accept to receive emails from ACM.
ACM History Committee: Fellowships in ACM History Proposals due: March 1, 2018 The Association for Computing Machinery, founded in 1947, is the oldest and largest educational and scientific society dedicated to the computing profession, and today has mDetails…
New concise book on RISC-V architecture available
Book Release: Blocks and Chains: Introduction to Bitcoin, Cryptocurrencies, and Their Consensus Mechanisms
Blocks and Chains: Introduction to Bitcoin, Cryptocurrencies, and Their Consensus Mechanisms: The new field of cryptographic currencies and consensus ledgers, commonly referred to as blockchains, is receiving increasing interest from various different communities. These communities are very diverse and amongst others include: technical enthusiasts, activist groups, researchers from various disciplines, startups, large enterprises, public authorities, banks, financial regulators, business men, investors, and also criminals. The scientific community adapted relatively slowly to this emerging and fast-moving field of cryptographic currencies and consensus ledgers. This was one reason that, for quite a while, the only resources available have been the Bitcoin source code, blog and forum posts, mailing lists, and other online publications. Also the original Bitcoin paper which initiated the hype was published online without any prior peer review. Following the original publication spirit of the Bitcoin paper, a lot of innovation in this field has repeatedly come from the community itself in the form of online publications and online conversations instead of established peer-reviewed scientific publishing. On the one side, this spirit of fast free software development, combined with the business aspects of cryptographic currencies, as well as the interests of today’s time-to-market focused industry, produced a flood of publications, whitepapers, and prototypes. On the other side, this has led to deficits in systematization and a gap between practice and the theoretical understanding of this new field. This book aims to further close this gap and presents a well-structured overview of this broad field from a technical viewpoint. The archetype for modern cryptographic currencies and consensus ledgers is Bitcoin and its underlying Nakamoto consensus. Therefore we describe the inner workings of this protocol in great detail and discuss its relations to other derived systems.
On-Chip Networks, Second Edition (Jerger/Krishna/Peh): This book targets engineers and researchers familiar with basic computer architecture concepts who are interested in learning about on-chip networks. This work is designed to be a short synthesis of the most critical concepts in on-chip network design. It is a resource for both understanding on-chip network basics and for providing an overview of state-of-the-art research in on-chip networks. We believe that an overview that teaches both fundamental concepts and highlights state-of-the-art designs will be of great value to both graduate students and industry engineers. While not an exhaustive text, we hope to illuminate fundamental concepts for the reader as well as identify trends and gaps in on chip network research.
The MICRO Test of Time (ToT) Award Committee is soliciting nominations for the third MICRO ToT Award to be given at the International Symposium on Microarchitecture in October 2017, to be held in Boston, MA, USA. This recognizes the most influential papers published in past MICRO conferences that have had significant impact in the field.
Understanding and implementing the brain’s computational paradigm is the one true grand challenge facing computer researchers. Not only are the brain’s computational capabilities far beyond those of conventional computers, its energy efficiency is truly remarkable. This book, written from the perspective of a computer designer and targeted at computer researchers, is intended to give both background and lay out a course of action for studying the brain’s computational paradigm. It contains a mix of concepts and ideas drawn from computational neuroscience, combined with those of the author. As background, relevant biological features are described in terms of their computational and communication properties. The brain’s neocortex is constructed of massively interconnected neurons that compute and communicate via voltage spikes, and a strong argument can be made that precise spike timing is an essential element of the paradigm Drawing from the biological features, a mathematics-based computational paradigm is constructed. The key feature is spiking neurons that perform communication and processing in space-time, with emphasis on time. In these paradigms, time is used as a freely available resource for both communication and computation. Neuron models are first discussed in general, and one is chosen for detailed development. Using the model, single-neuron computation is first explored. Neuron inputs are encoded as spike patterns, and the neuron is trained to identify input pattern similarities. Individual neurons are building blocks for constructing larger ensembles, referred to as “columns”. These columns are trained in an unsupervised manner and operate collectively to perform the basic cognitive function of pattern clustering. Similar input patterns are mapped to a much smaller set of similar output patterns, thereby dividing the input patterns into identifiable clusters. Larger cognitive systems are formed by combining columns into a hierarchical architecture. These higher level architectures are the subject of ongoing study, and progress to date is described in detail in later chapters. Simulation plays a major role in model development, and the simulation infrastructure developed by the author is described.
DEADLINE: Travel grant application form must be received by 11:59pm EDT, May 8, 2017 With generous support from the U.S. National Science Foundation, ACM SIGARCH, and IEEE TC on Computer Architecture, ISCA-44 will offer travel grants for students to deDetails…
To put future research in Persistent Memory software and hardware on a firmer footing, researchers from Wisconsin and HP Labs have developed a PM benchmark suite called WHISPER whose open source is available now. They took benchmarks that used PM directly (echo, n-store), via libraries (reds, c-tree, hashmap, vacation, memcached) and as a file system (nfs, exim, mysql) and modified them so that accesses use volatile memory except as necessary to provide consistent state for crash recovery.
The IEEE TCCA Young Computer Architect Award recognizes outstanding research contributions by an individual in the field of Computer Architecture, who received his/her PhD degree within the last 6 years. The Award will be presented at the Awards Banquet at the 2017 International Symposium on Computer Architecture (ISCA). The IEEE Computer Society administers the award.
Call for Nominations: ACM SIGARCH Student Scholarships for ACM’s Celebration of 50 Years of the ACM Turing Award
ACM SIGARCH has a limited number of scholarships to award to worthy students to attend the Celebration of 50 Years of the ACM Turing Award 23-24 June 2017 at the Westin St. Francis in San Francisco, CA. Each scholarship includes 2 nights at the Westin St. Francis Hotel in San Francisco and up to $900 to help offset the cost of travel and subsistence (Students will receive a check from ACM upon submission of receipts for travel).
SIGARCH expresses concerns about the presidential executive order restricting entry into the USA.