May 4, 2021
DRAMSec: 1st Workshop on DRAM Security 2021
Co-located with ISCA 2021 (virtual)
Submissions Due: May 4, 2021
We are soliciting papers on attacks and defenses on current and future DRAM technologies. The program committee will favor papers that bring new insights, debunk previously held beliefs, re-visit assumptions, present new attacks and defenses, or put forward controversial points of view. We also consider position papers especially from industry that outline design and process challenges affecting DRAM security, new forms of secure DRAM, or describe state-of-the-art DRAM defenses.
Submissions must be original, unpublished work, and not under consideration at another conference or journal. The authors must use the DRAMSec hotcrp for submitting their papers. Papers must be formatted for US letter (not A4) size paper using the Microsoft Word or LaTeX templates provided on the IEEE website. The length of the submitted papers should be 5 pages at maximum, excluding references. Appendices count towards the page limit, while the main body of the paper should be self-contained. Paper submissions will go through a double-blind reviewing process by the DRAMSec program committee and should not include author names or affiliations. At least one author for each accepted paper is required to present the paper at the workshop.
We expect that at least some papers at DRAMSec would represent “work-in-progress” projects. Therefore, authors of published papers could choose to extend their work to full-length conference papers later.
Topics of interest
- New possible forms of attacks on DRAM that may affect future DRAM technologies
- New insights in reverse engineering DRAM functionality related to security including but not limited to in-DRAM defenses
- Characterizing the susceptibility of different types of DRAM to attacks
- Novel defenses and mitigations
- Pitfalls or debunking previous attacks or defenses
- Re-engineering software systems to handle faulty DRAM
- Novel Rowhammer exploitation techniques
- Exploitation of other DRAM reliability issues
- Design and process challenges to DRAM security
- Characterizations of state-of-the-art security defenses deployed in DRAM at large