H2RC @ SC2026

12th International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC 2026)
Co-located with Supercomputing 2025
November 16, 2026
http://h2rc.cse.sc.edu

High-performance computing is entering a post-exascale era in which scalable performance is constrained not only by peak floating-point capability, but also by power delivery, energy efficiency, cooling, data movement, memory hierarchy, and sustained utilization of increasingly heterogeneous resources. At the same time, HPC workloads are broadening to include coupled simulation, AI, data analytics, streaming data, and urgent decision workflows, each with distinct requirements for precision, locality, latency, throughput, and programmability.

Spatial and reconfigurable architectures offer a compelling path forward. FPGAs remain an important example, enabling application-specific datapaths and communication patterns that can improve performance and efficiency. The design space is now expanding to include AI Engine arrays, coarse-grained reconfigurable architectures (CGRAs), dataflow and streaming processors, wafer-scale systems, and other domain-specialized spatial fabrics. These architectures promise gains not only in raw performance, but also in performance per watt, data-movement efficiency, and the ability to adapt computation to diverse and evolving workloads.

Realizing this potential requires advances across the hardware/software stack. The central challenge is how programming models, compilers, intermediate representations, placement and scheduling techniques, runtime systems, autotuning, and performance/energy models can map full HPC applications onto emerging spatial fabrics at scale. With this in mind, the 12th Workshop on Heterogeneous High-performance Reconfigurable Computing brings together researchers and practitioners in HPC, computer architecture, compilers, and heterogeneous systems to share experiences, demonstrate new techniques, and identify future opportunities and research needs for high-performance spatial and reconfigurable computing.

Submission Tracks and Contribution Selection

Submissions are solicited for two tracks:
Track 1: Full-length papers of 4 to 10 pages, excluding references, for oral presentation and publication in the SC Workshop Proceedings.
Track 2: Extended abstracts / talk proposals of up to 2 pages, excluding references, for oral presentation without publication in the SC Workshop Proceedings.

Track 1 is intended for technical papers containing substantial implementation detail, methodological contribution, evaluation, and analysis of experimental results. Track 1 is well suited for academic, national laboratory, and industrial authors who seek peer-reviewed archival publication in the SC Workshop Proceedings.

Track 2 is intended for industrial contributions describing new capabilities, products, platforms, tools, or application opportunities, as well as work-in-progress presentations from academic, national laboratory, and industrial authors. The emphasis of Track 2 is to stimulate discussion with the workshop audience. Accepted Track 2 extended abstracts will be made available on the workshop website but will not appear in the SC Workshop Proceedings.

Each submission will receive at least three peer reviews by members of the technical program committee.

Using the TPC reviews, the organizing committee will select contributions for presentation based on scientific merit, technical quality, interest, and relevance to the HPC community.

Topics of Interest

Submissions are solicited that explore the state of the art in reconfigurable, spatial, and dataflow architectures for heterogeneous high-performance computing. Relevant platforms include, but are not limited to, FPGAs, AI Engine arrays, coarse-grained reconfigurable architectures, compiler-scheduled spatial architectures, streaming and dataflow processors, wafer-scale systems, and emerging commercial or experimental spatial fabrics.

Submissions may consider these architectures as standalone accelerators, as components of heterogeneous nodes, as distributed or composable compute fabrics, or as dynamically adaptable resources in larger HPC systems, clouds, and data centers. Work investigating their integration with CPUs, GPUs, APUs, DPUs, NPUs, SmartNICs, memory systems, networks, and storage systems is particularly welcome.

Submissions may report on theoretical or applied research, implementation case studies, benchmarks, standards, tools, experience reports, or any other work that advances understanding of heterogeneous high-performance reconfigurable and spatial computing. A non-exhaustive list of topics of interest includes:

• Performance and energy efficiency of HPC applications on FPGAs, AI Engines, CGRAs, dataflow processors, wafer-scale systems, and other spatial architectures
• Compilation techniques for spatial and reconfigurable architectures, including scheduling, placement, routing, mapping, graph lowering, autotuning, design-space exploration, MLIR/LLVM-based flows, and domain-specific compiler frameworks
• Runtime systems, resource management, dynamic adaptation, and utilization-aware scheduling for heterogeneous spatial fabrics
• Programming models, libraries, DSLs, and portability layers for spatial and reconfigurable computing
• Application studies in simulation, AI for science, sparse and irregular computation, stencils, linear algebra, signal processing, graph analytics, compression, visualization, and data-intensive workflows
• System integration of spatial accelerators in HPC systems, clouds, composable infrastructures, data centers, storage systems, and networks
• Performance, power, thermal, reliability, and cost modeling for heterogeneous reconfigurable and spatial systems
• Benchmarks, proxy applications, reproducibility, and evaluation methodologies
• Debugging, verification, profiling, and performance-analysis tools for spatial and reconfigurable architectures
• Hardware/software co-design for post-exascale HPC and AI workloads
• Experience reports on emerging commercial, prototype, or experimental spatial/dataflow platforms, including lessons learned and open challenges

Important dates:

• Submission Deadline: August 5, 2026
• Acceptance Notification: September 4, 2026
• Camera-ready Manuscripts Due: September 25, 2026
• Workshop Date: November 16, 2026

Submission link: https://bit.ly/h2rc2026

Organizers:
Jason D. Bakos, University of South Carolina
Andrew Schmidt, AMD
Suhaib A. Fahmy, King Abdullah University of Science and Technology