Call for Papers:

H2RC Workshop

Abstract or Paper Registration Deadline
August 7, 2021
Final Submission Deadline
August 7, 2021

The Seventh International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) will be held on Monday, November 15, 2021. Accepted papers will be indexed and published in the IEEE Digital Library though TCHPC and invited to submit extended manuscript to a special issue of the Elsevier Journal of Parallel and Distributed Computing on H2RC 2021.

Submission link

As conventional von-Neumann architectures are suffering from rising power densities, we are facing an era with power, energy efficiency, and cooling as first-class constraints for scalable HPC. FPGAs can tailor the hardware to the application, avoiding overheads and achieving higher hardware efficiency than general-purpose architectures. Leading FPGA manufacturers have recently made a concerted effort to provide a range of higher-level, easier-to-use high-level programming models for FPGAs, and much of the work in FPGA-based deep learning is built on these frameworks.

Such initiatives are already stimulating new interest within the HPC community around the potential advantages of FPGAs over other architectures. With this in mind, this workshop, now in its sixth year, brings together HPC and heterogeneous-computing researchers to demonstrate and share experiences on how newly-available high-level programming models, including OpenCL, are already empowering HPC software developers to directly leverage FPGAs, and to identify future opportunities and needs for research in this area.

Submission Tracks and Contribution Selection
Submissions are solicited for two tracks:

Track 1: Full-length papers (10 pages excluding references) for 25-minute oral presentation and publication in proceedings archived by IEEE.
Track 2: Extended abstracts / talk proposals (4 pages) for 15-minute oral presentation without publication.

Track 1 is targeted for technical papers containing a high level of implementation detail and analysis and discussion of experimental results. Track 1 is suited for members of the academic and national lab community who prefer to have their work peer-reviewed, indexed and archived by IEEE.

Track 2 is targeted for industrial contributions that describe new capabilities and opportunities offered by emerging technologies and products, or work in progress presentations by the academic and national lab community. The emphasis of this track is to initiate a discussion with the audience.

All submissions are reviewed and evaluated by at least three members of our technical program committee.  From the TPC evaluation of each submission, the organizing committee will select papers for presentation based on a criteria that is equally weighted between scientific merit and level of interest and relevance to the HPC community.

Submission Topics
Submissions are solicited that explore the state of the art in the use of FPGAs in heterogeneous high-performance compute architectures and, at a system level, in data centers and supercomputers. FPGAs may be considered from either or both the distributed, parallel and composable fabric of compute elements or from their dynamic reconfigurability. We particularly encourage submissions which focus on the mapping of algorithms and applications to heterogeneous FPGA-based systems as well as the overall impact of such architectures on the compute capacity, cost, power efficiency, and overall computational capabilities of data centers and supercomputers.  Submissions may report on theoretical or applied research, implementation case studies, benchmarks, standards, or any other area that promises to make a significant contribution to our understanding of heterogeneous high-performance reconfigurable computing and will help to shape future research and implementations in this domain. A non-comprehensive list of potential topics of interest is given below:

  1. Improvement of performance or efficiency of HPC or data center applications with FPGAs
  2. System integration of FPGAs in clouds and HPC systems
  3. Leveraging reconfigurability
  4. Benchmarks
  5. Programming languages, tools, and frameworks
  6. Future-gazing

Submission Guidelines

Full papers (Track 1)Authors should submit original contributions of up to 10 pages (excluding references) in PDF format using the SC21 Linklings portal (, which is also linked from the H2RC website ( Submissions must be formatted as single-spaced, double-column, A4 pages without page numbers following the IEEE conference proceedings format, including figures, tables, and references. H2RC uses a single blind review process. We support the SC reproducibility initiative and highly encourage authors to add an artifact description/artifact evaluation appendix of up to 2 additional pages to their paper. All accepted papers will be published in the IEEE TCHPC Proceedings in the IEEE Xplore digital library.

Talk proposals (Track 2):To apply for a talk authors should submit a 4-page extended abstract. The extended abstract will be peer-reviewed and used for deciding on the acceptance of a presentation assignment of a presentation slot, but will not be published in the proceedings. The papers shall follow the same formatting instructions as the full papers and have also to be submitted using the Linklings system.

Important Dates
Submission Deadline:                                    August 7, 2021
Acceptance Notification:                                October 1, 2021
Camera-ready Manuscripts Due:                   October 15, 2021
Workshop Date:                                             November 15, 2021

Workshop Format
H2RC is a full-day Monday workshop.  It will be comprised of:

  • Keynote and invited talks
  • Talks selected among paper submissions
  • Panel discussion on research opportunities and needs

Workshop Organizers
Jason D. Bakos, University of South Carolina
Franck Capello, Argonne National Lab
Torsten Hoefler, ETH Zurich
Ken O’Brien, Xilinx
Christian Plessl, Paderborn University