Call for Papers:

Heterogeneous High-performance Reconfigurable Computing (H2RC 2024)

Abstract or Paper Registration Deadline
August 7, 2024
Final Submission Deadline
August 7, 2024

10th International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC 2024)
co-located with SC 2024
Half Day Friday, 22nd November

As conventional von-Neumann architectures are suffering from rising power densities, we are facing an era with power, energy efficiency, and cooling as first-class constraints for scalable HPC. FPGAs can tailor the hardware to the application, avoiding overheads and achieving higher hardware efficiency than general-purpose architectures. Leading FPGA manufacturers have recently made a concerted effort to provide a range of higher-level, easier-to-use high-level programming models for FPGAs, and much of the work in FPGA-based deep learning is built on these frameworks.

Such initiatives are already stimulating new interest within the HPC community around the potential advantages of FPGAs over other architectures. With this in mind, this workshop, now in its ninth year, brings together HPC and heterogeneous computing researchers to demonstrate and share experiences on how newly-available high-level programming models are already empowering HPC software developers to directly leverage FPGAs and to identify future opportunities and needs for research in this area.

Submissions are solicited for two tracks:

Track 1: Full-length papers (8 pages, excluding references) for oral presentation and publication in proceedings archived by IEEE.

Track 2: Extended abstracts / talk proposals (2 pages, excluding references) oral presentation without publication.

Submission Topics
Submissions are solicited that explore the state of the art in the use of FPGAs in heterogeneous high-performance compute architectures and, at a system level, in data centers and supercomputers. FPGAs may be considered from either or both the distributed, parallel and composable fabric of compute elements or from their dynamic reconfigurability. Submissions investigating the use of FPGAs in combination with other devices such as CPU/GPU/APU/DPU are particularly welcomed.

Submissions may report on theoretical or applied research, implementation case studies, benchmarks, standards, or any other area that promises to make a significant contribution to our understanding of heterogeneous high-performance reconfigurable computing and help to shape future research and implementations in this domain. A non-comprehensive list of potential topics of interest is given below:

  1. Use of FPGAs to improve performance or efficiency of HPC or data center applications
  2. System integration of FPGAs in clouds and distributed HPC systems
  3. Leveraging reconfigurability
  4. Benchmarks
  5. Programming languages, tools, and frameworks
  6. Future-gazing

Important dates:

  • Submission Deadline: August 7
  • Acceptance Notification: September 6
  • Camera-ready Manuscripts Due: September 27 Workshop Date: November 22

Submission link:

For further information and submission guidelines please visit

Workshop Organizers:
Jason D. Bakos, University of South Carolina
Franck Capello, Argonne National Lab
Torsten Hoefler, ETH Zurich
Ken O’Brien, AMD
Christian Plessl, Paderborn University
Melissa Crawley Smith, Clemson University