July 27, 2018
August 3, 2018
25th International Symposium on High Performance Computer Architecture (HPCA)
February 16-20, 2019
Washington, D.C., USA
Abstract registration deadline: July 27, 2018 @ 11:59 PM EDT
Submission deadline: Aug 3, 2018 @ 11:59 PM EDT
The industry session submission deadline is the same as the regular session
The International Symposium on High-Performance Computer Architecture includes an industry session on the architecture of future systems technologies. The objective of this session is to provide a unique forum for industry participants to present their perspective on technical challenges facing future systems and discuss potential solutions. The discussion in this forum is expected to educate the wider computer architecture community on the challenges facing the industry and to encourage them to investigate solutions. The session will include a small number of papers selected based on depth and relevance to the HPCA audience.
Architects, designers and developers involved in some aspect of industrial computer systems design and development are invited to submit a paper describing new challenges, issues, and opportunities in the next-generation computer systems. The paper needs to provide insights, results, etc. that are unique to industry, which makes it clearly distinguishable from a regular paper*.
* Industry session papers should have authors from industry but may also have academic co-authors if the contributions are clearly from the industry.
Authors should submit an abstract by July 27, 2018 11:59 PM EDT. They should submit the full version of the paper by August 3, 2018, 11:59 PM EDT. No extensions will be granted. The full version should be a PDF file following the submission guidelines that will be made available at the submission website. Papers should be submitted for double-blind review. See the HPCA 2019 website: http://hpca2019.seas.gwu.edu/ for additional information about HPCA 2019 and submission details.
Topics of interest include, but are not limited to:
– Processor, cache and memory architectures
– Parallel/multi-core architectures
– Domain-specific accelerators
– Power-efficient architectures
– Dependable/secure architectures
– Analysis and exploitation of security vulnerabilities
– High-performance I/O systems
– Embedded, IoT, reconfigurable, and heterogeneous architectures
– Interconnect and network interface architectures
– Architectures for cloud, HPC, and data centers
– Innovative hardware/software trade-offs
– Impact of compilers and system software on architecture
– Performance/power modeling and evaluation
– Architectures for emerging technology and applications
Ahmed Louri (GWU)
Guru Prasadh Venkataramani (GWU)
Industry Session Chairs:
Christopher Hughes (Intel Labs)
Niti Madan (AMD Research)