Final Submission Deadline
November 6, 2015

Submitted by Oscar Palomar

9th International Workshop on Programmability and
Architectures for Heterogeneous Multicores (MULTIPROG-2016)

in conjunction with HiPEAC 2016
Prague, Czech Republic
January 18, 2016
Computer manufacturers have embarked on the many-core roadmap, promising to add
more and more cores/hardware threads on their chips. The ever-increasing number
of cores and heterogeneity in architectures has placed new burdens on the
programming community. Software needs to be parallelized and optimized for
accelerators such as GPUs in order to take advantage of the new breed of
multi-/many-core computers. As a result, progress in how to easily harness the
computing power of multi-core architectures is in great demand.

The ninth edition of the MULTIPROG workshop aims to bring together researchers
interested in programming models, runtimes, and computer architecture. The
workshop’s emphasis is on heterogeneous architectures and covers issues such
– How can future parallel programming models improve software productivity?
– How should compilers, runtimes and architectures support programming
models and emerging applications?
– How to design efficient data structures and innovative algorithms?

MULTIPROG is intended for quick publication of early results, work-in-progress,
etc., and is not intended to prevent later publication of extended papers.
Informal proceedings with accepted papers will be made available at the
workshop and online at the workshop’s web page.

Papers are sought on topics including, but not limited to:
1) Multi-core architectures
– Architectural support for compilers/programming models
– Processor (core) architecture and accelerators, in particular GPUs
– Memory system architecture
– Performance, power, temperature, and reliability issues
2) Heterogeneous computing
– Algorithms and data structures for heterogeneous systems
– Applications for heterogeneous computing and real-time graphics
3) Programming models for multi-core architectures
– Language extensions
– Run-time systems
– Compiler optimizations and techniques
4) Benchmarking of multi-/many-core architectures
– Tools for discovering and understanding parallelism
– Tools for understanding performance and debugging
– Case studies and performance evaluation

Full paper submission: Extended until November 6, 2015
Author notification: December 4, 2015

Submissions should not exceed 12 pages and should be formatted according
to the LNCS format for CS Proceedings. This limit includes text, figures,
tables and references. Further submission instructions and templates are
available at the workshop website.

Workshop chairs:
– Miquel Pericàs, Chalmers University of Technology, Sweden
– Vassilis Papaefstathiou, Chalmers University of Technology, Sweden
– Oscar Palomar, Barcelona Supercomputing Center, Spain
– Ferad Zyulkyarov, Barcelona Supercomputing Center, Spain

Steering committee:
– Eduard Ayguade, UPC/Barcelona Supercomputing Center, Spain
– Benedict R. Gaster, Qualcomm, USA
– Lee Howes, Qualcomm, USA,
– Per Stenstrom, Chalmers University of Technology, Sweden
– Osman Unsal, Barcelona Supercomputing Center, Spain

Program committee:
– Abdelhalim Amer, Argonne National Lab, USA
– Ali Jannesari, TU Darmstadt, Germany
– Avi Mendelson, Technion, Israel
– Christos Kotselidis, University of Manchester, UK
– Daniel Goodman, Oracle, UK
– Dong Ping Zhang, AMD, USA
– Håkan Grahn, Blekinge TH, Sweden
– Hans Vandierendonck, Queen’s University Belfast, UK
– Kenjiro Taura, University of Tokyo, Japan
– Luigi Nardi, Imperial College London, UK
– Naoya Maruyama, RIKEN AICS, Japan
– Oscar Plata, University of Malaga, Spain
– Pedro Trancoso, University of Cyprus, Cyprus
– Polyvios Pratikakis, FORTH-ICS, Greece
– Roberto Gioiosa, PNNL, USA
– Ruben Titos, BSC, Spain
– Sasa Tomic, IBM Research, Switzerland
– Simon McIntosh-Smith, University of Bristol, UK
– Timothy G. Mattson, Intel, USA
– Trevor E. Carlson, Uppsala University, Sweden