Call for Papers:

Workshop on Accelerators and Hybrid Exascale Systems

Final Submission Deadline
January 13, 2017

The Seventh International Workshop on Accelerators and Hybrid Exascale Systems (AsHES)
in conjunction with IPDPS’17
Orlando, Florida, USA
May 29, 2017

Paper Submission: Jan. 13, 2017 (AoE)
Paper Notification: Feb. 15, 2017
Camera-Ready: Feb. 25, 2017

Current and emerging systems are deployed with heterogeneous architectures and accelerators of more than one type (e.g., GPGPU, Intel® Xeon Phi™, FPGA) along with hybrid processors of both lightweight and heavyweight cores (e.g., APU, big.LITTLE). Such architectures also comprise hybrid memory systems equipped with stacked/hierarchical memory and non-volatile memory in addition to regular DRAM. Programming such a system can be a real challenge along with locality,
scheduling, load balancing, concurrency and so on.

This workshop focuses on understanding the implications of accelerators and heterogeneous designs on the hardware systems, porting applications, performing compiler optimizations, and developing programming environments for current and emerging systems. It seeks to ground accelerator research through studies of application kernels or whole applications on such systems, as well as tools and libraries that improve the performance and productivity of applications on these systems. The goal of the workshop is to bring together researchers and practitioners who are involved in application studies for accelerators and other heterogeneous systems, to learn the opportunities and challenges in future design trends for HPC applications and systems.

Topics of interest for workshop submissions include (but are not limited to):
– Strategies for programming heterogeneous systems using high-level models such as OpenMP and OpenACC, and low-level models such as OpenCL, CUDA;
– Methods and tools to tackle challenges in scientific computing at extreme scale;
– Strategies for application behavior characterization and performance optimization for accelerators;
– Techniques for optimizing kernels for execution on GPGPU, Intel Xeon Phi and future heterogeneous platforms;
– Models of application performance on heterogeneous and accelerated HPC systems;
– Compiler Optimizations and tuning heterogeneous systems including parallelization, loop transformation, locality optimizations, Vectorization;
– Implications of workload characterization in heterogeneous and accelerated architecture design;
– Benchmarking and performance evaluation for accelerators;
– Tools and techniques to address both performance and correctness to assist application development for accelerators and heterogeneous processors;
– System software techniques to abstract application domain-specific functionalities for accelerators;

Keynote Speaker:
Tim Mattson (Intel) will give a keynote speech at AsHES 2017.

Papers should present original research and should provide sufficient background material to make them accessible to the broader community. Submitted manuscripts may not exceed 10 single-spaced double-column pages using 10-point size font on 8.5×11 inch pages (IEEE conference style), including figures, tables, and references. See the style templates for latex or word for details.

Submissions will be judged based on relevance, significance, originality, correctness and clarity.
Submission site:

The proceedings of this workshop will be published electronically together with IPDPS proceedings via the IEEE Xplore Digital Library.

General Chair:
Sunita Chandrasekaran, University of Delaware, USA

Program Co-Chairs:
Antonio J. Peña, Barcelona Supercomputing Center, Spain
Sangmin Seo, Argonne National Laboratory, USA

Program Committee:
Ashwin Aji, AMD, USA
James Beyer, NVIDIA Corporation, USA
Huimin Cui, Institute of Computing Technology, CAS
Anthony Danalis, University of Tennessee, USA
Khaled Hamidouche, The Ohio State University, USA
Jeff Hammond, Intel Labs, USA
Siva Kumar Sastry Hari, NVIDIA Corporation, USA
Hennry Jin, NASA, USA
Guido Juckeland, HZDR, Germany
Sriram Krishnamoorthy, Pacific Northwest National Laboratory, USA
Seyong Lee, Oak Ridge National Laboratories, USA
Dong Li, University of Calfornia, Merced, USA
John Lidel, Texas Tech University, USA
Piotr Luszczek, University of Tennessee, USA
Naoya Maruyama, RIKEN AICS, Japan
Stephen Olivier, Sandia Nationl Lab, USA
Kelly Shaw, University of Richmond, USA
Xipeng Shen, North Carolina State University, USA
Min Si, Argonne National Laboratory, USA
Bronis de Supinski, Lawrence Livermore National Laboratory, USA
Hao Wang, Virginia Tech, USA
Yongpeng Zhang, Stone Ridge Technology, USA

Steering Committee:
Pavan Balaji, Argonne National Laboratory, USA
Yunquan Zhang, Chinese Academy of Sciences, China
Satoshi Matsuoka, Tokyo Institute of Technology, Japan
Jiayuan Meng, Argonne National Laboratory, USA
Xiaosong Ma, Qatar Computing Research Institute, Qatar
Barbara Chapman, University of Houston, USA
Guang R. Gao, University of Delaware, USA
Xinmin Tian, Intel, USA
Michael Wong, IBM, Canada
James Dinan, Intel Corporation

Please send any queries about the AsHES workshop to