Call for Papers:

Workshop on AI-assisted Design for Architecture

Abstract or Paper Registration Deadline
May 17, 2019
Final Submission Deadline
May 17, 2019

The 2nd International Workshop on AI-assisted Design for Architecture (AIDArc 2019)
in conjunction with ISCA 2019
Phoenix, USA
June 22, 2019

Given the success of AIDArc 2018 and the significantly increased interest in utilizing AI to improve computer architecture in the past year, we are thrilled to organize AIDArc 2019, held in conjunction with ISCA-46.

Recent advancements in machine learning algorithms, fueled by increased data availability and high-performance computing infrastructure, have led to successful applications of machine learning (and AI in general) in numerous disciplines and domains. Although much attention has been drawn in the computer architecture community on accelerating machine learning, limited research has been conducted to utilize the power of AI/ML to help architects design better computer architectures and systems.

The AIDArc Workshop is intended to bring together researchers, scientists and practitioners across academia and industry, to share early discoveries, successful examples, and opinions on opportunities and challenges regarding utilizing AI to assist computer architecture designs. Research along this line may potentially transform the way computers are designed and optimized. It may also lead to interesting “self-evolving architecture”, where AI helps to speed up computers which, in turn, are used to speed up the AI.

Topics of submitted papers include, but not limited to, the exploration of artificial intelligence in assisting the design and optimization of:
– Various components of computer system architecture, e.g., branch predictor, cache, memory, I/O, interconnection networks, etc.
– Various design objectives of computer system architecture, e.g., power/energy, performance, resource, reliability, security, etc.
– Different types of computer architectures and systems, e.g., embedded/mobile/wearable devices, CPUs, GPUs, special-purpose accelerators, datacenters, HPCs, etc.
– Interaction of computer architecture with other layers, e.g., operating systems, compilers, circuit-level designs, etc.

Papers will be reviewed based on originality, novelty, technical strength, presentation quality, correctness and relevance to the workshop scope. Early but novel works on related topics are highly encouraged.

ORGANIZERS:
Lizhong Chen, Oregon State University, chenliz@oregonstate.edu