Workshop on Architectural Research Prototyping

Final Submission Deadline
April 10, 2015

Submitted by Christopher Batten

WARP: 6th Workshop on Architectural Research Prototyping
Co-located with ISCA’15
Portland, Oregon, USA
Sunday, June 14th, 2015
Building prototype systems can be one of the best ways to validate
assumptions, gain intuition about practical design issues, and
provide platforms for future software research. While the research
ideas behind these prototypes can be published in top-tier
conferences, there are not many venues suitable for focusing on the
actual prototype itself. At the same time, building an FPGA, ASIC, or
full-custom computer architecture prototype is a non-trivial endeavor
and requires a significant financial and time commitment. This
workshop is intended as a forum for the builders in our community to
share their practical on-the-ground experiences, to provide a status
update on their progress, and to convey insights for those
considering prototyping their ideas.

This half-day workshop will be held on Sunday, June 14th, 2015,
co-located with ISCA-42 in Portland, OR. The workshop will primarily
include presentations selected by the technical program committee
based on extended abstract submissions.

We invite submissions on all aspects of building prototype systems
for computer architecture research. Submissions can be based on new
or pending prototypes that have not been discussed in any other
venue, or submissions can focus on the practical prototyping
implications of a previously published research paper. Submissions
more in the spirit of a short position paper are also encouraged.

Topics of particular interest include, but are not limited to:

– Status updates on FPGA, ASIC, or full-custom prototypes
that have been recently constructed or are under construction

– Implementation technology trade-offs (FPGAs, ASICs, full-custom)

– Practical guidance on what works and what doesn’t,
including strategies for:
o High-level specification
o Register-transfer-level implementation
o Pre- and post-construction verification
o Packaging and board design
o Managing complex electronic design automation toolflows

– Practical advice on managing the increasing design complexity
inherent in building computer architecture research prototypes
that integrate general-purpose processors and memory systems with
specialized accelerators

– How to balance the often conflicting goals of prototypes as
research vehicles containing novel architectural mechanisms vs.
prototypes as high-performance software development platforms

– How to balance student’s thesis goals vs. engineering work
– How to secure funding for building prototypes

Participation is encouraged for all members of the computer
architecture community, including those considering embarking on a
prototyping effort or those who strongly disagree with the need to
build prototypes.

Participants are invited to submit an extended abstract of up to two
pages (single or double column, 10pt, single spaced). Please include
the authors’ names, affiliations, and clearly reference any previous
publications that were based on the prototype. Submissions must be in
PDF format and submitted according to the instructions posted on the
WARP website.

Participants may also include an appendix of any length. However, we
will not promise to read the appendix, so the extended abstract
should stand alone as a coherent description of what you will discuss
in your talk. The appendix can provide additional details such as
device micrographs or more detailed results.

Extended abstracts and presentation slides will only be posted on the
workshop website with permission of the authors. Authors should feel
free to submit work in progress or work under review (where
permitted) without fear of double publication issues.

– Submission Deadline: April 10, 2015
– Notification of Selection: April 20, 2015
– Final Abstract Submission: May 22, 2015

Workshop chairs:
– Christopher Batten, Cornell University
– Dave Wentzlaff, Princeton University

Program Committee:
– David Brooks, Harvard University
– Steve Keckler, NVIDIA/University of Texas at Austin
– Mark Oskin, University of Washington
– Jose Renau, University of California, Santa Cruz