Workshop on Energy Efficient SuperComputing

Final Submission Deadline
August 18, 2015

Submitted by Joseph Manzano

3rd International Workshop on Energy Efficient SuperComputing (E2SC)
in conjunction with SC’15
Austin, Texas, USA
November 15-20, 2015
With Exascale systems on the horizon, we will be ushering in an era with power
and energy consumption as a key concern for scalable computing. To achieve
viable high performance, a combination of evolutionary and revolutionary
methods is required with a stronger integration among hardware features, system
software and applications. Equally important are the capabilities for
fine-grained spatial and temporal measurement and control to facilitate energy
efficient computing across all layers. Current approaches for energy efficient
computing rely heavily on power efficient hardware in isolation. However, it is
pivotal for hardware to expose mechanisms for energy efficiency to optimize
power and energy consumption for various workloads and to reduce data motion,
a major component of energy use. At the same time, high fidelity measurement
techniques, typically ignored in data-center level measurement, are of high
importance for scalable and energy efficient inter-play at different layers of
application, system software and hardware.

This workshop seeks to address the important energy efficiency aspects in the
HPC community that have not been previously addressed by aspects covered in the
data center or cloud computing communities. Emphasis is given to an
application’s view related to significant energy efficiency improvements as
well as to the required hardware/software stack that must include necessary
power and performance measurement, and analysis harnesses.

Current tools are often limited by hardware capabilities and their lack of
information about the characteristics of a given workload/application. In the
same manner, hardware techniques, like dynamic voltage frequency scaling, are
often limited by their granularity (very coarse power management) or by their
scope (a very limited system view). More rapid realization of energy savings
will require significant increases in measurement resolution and optimization
techniques. Moreover, the interplay between performance, power and reliability
add another layer of complexity to this already difficult group of challenges.

We encourage submissions in the following areas:
– Tools for power and energy analysis with different granularities and scope from
hardware (e.g., component, core, node, rack, system) or software views (e.g., threads,
tasks, processes, etc.) or both.
– Tools and techniques for measurement, analysis, and modeling of thermal
effects at different granularities (e.g., component, core, node, rack, system)
for large-scale systems.
– Techniques that enable power and energy optimizations at different scale levels
for HPC systems.
– Integration of power-aware technologies in applications and throughout the
software stack of HPC systems.
– Characterization of current state-of-the-art HPC systems and applications in terms
of power.
– Disruptive infrastructure hardware technologies for energy-efficient
– Analysis of future technologies that will provide improved energy consumption
and management on future HPC systems.

Paper Submission: August 18, 2015
Paper Notification: September 25, 2015
Final Papers Due: October 9, 2015

Papers should not exceed ten single-space pages (including figures, tables
and references) using a 10-point on 8.5×11-inch pages (US Letter).
Templates can be found in:

Submissions will be judged on correctness, originality, technical strength,
significance, presentation quality and appropriateness. Submitted papers
should not have appeared in or should not be under consideration for
another venue. A full peer-review processes will be followed with each
paper being reviewed by at least 3 members of the program committee.
Submissions will be made through EasyChair

General Chairs:
Kirk Cameron, Virginia Tech, USA
Adolfy Hoisie, Pacific Northwest National Lab, USA
Darren Kerbyson, Pacific Northwest National Lab, USA
David Lowenthal, Arizona State University, USA
Dimitrios S. Nikolopoulos, Queen’s University of Belfast, UK
Sudha Yalamanchili, Georgia Institute of Technology, USA

Program Co-Chairs:
Laura Carrington, San Diego Supercomputing Center, USA
Joseph Manzano, Pacific Northwest National Lab, USA

Publicity Chair:
Andres Marquez, Pacific Northwest National Laboratory, USA

European Liaison:
Michele Weiland, EPCC, UK

Publication Chair:
Abhinav Vishnu, Pacific Northwest National Laboratory, USA

Onsite Coordination:
Kevin J. Barker, Pacific Northwest National Lab, USA

Program Committee:
Jee Choi Georgia Institute of Technology, USA
Pietro Cicotti San Diego Supercomputing Center, USA
Philippe Clauss University of Strasbourg, France
Joshua Fryman Intel, USA
Vladimir Getov University of Westminster, UK
Georg Hager Erlangen Regional Computing Center, Germany
Eric Van Hensbergen ARM Research, USA
Torsten Hoefler ETH Zurich, Switzerland
Hillery Hunter IBM Research, USA
Lennart Johnsson University of Houston, USA
Erwin Laure KTH/PDC Royal Institute of Technology, Sweden
Dong Li University of California Merced, USA
Satoshi Matsuoka Tokyo Institute of Technology, Japan
Leonid Oliker Lawrence Berkeley National Laboratory, USA
Scott Pakin Los Alamos National Laboratory, USA
Barry Rountree Lawrence Livermore National Laboratory, USA
Shuaiwen Song Pacific Northwest National Laboratory, USA