Workshop on Heterogeneous High-performance Reconfigurable Computing
September 1, 2017
September 1, 2017
Third International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC’17)
in conjunction with SC’17
November 17, 2017
Submission Deadline: September 1, 2017
Acceptance Notification: October 15, 2017
Camera-ready Manuscripts Due: November 4, 2017
Workshop Date: November 17, 2017
As conventional von-Neumann architectures are suffering from rising power densities, we are facing an era with power, energy efficiency, and cooling as first-class constraints for scalable HPC. FPGAs can tailor the hardware to the application, avoiding overheads and achieving higher hardware efficiency than general-purpose architectures. Leading FPGA manufacturers have recently made a concerted effort to provide a range of higher-level, easier to use high-level programming models for FPGAs.
Such initiatives are already stimulating new interest within the HPC community around the potential advantages of FPGAs over other architectures. With this in mind, this workshop, now in its third year, brings together HPC and heterogeneous-computing researchers to demonstrate and share experiences on legacy and new high-level programming models, optimizations specific to scientific computing and data analytics, tools for performance/energy improvements, FPGA computing in the cloud, and popular applications for reconfigurable computing such as machine learning and big data.
H2RC is a half-day Friday workshop. It will be comprised of a keynote, invited talks and talks selected from paper submissions.
Submissions are solicited that explore the state of the art in the use of FPGAs in heterogeneous high-performance computing architectures and, at a system level, in data centers and supercomputers. FPGAs may be considered from either or both the distributed, parallel and composable fabric of compute elements or from their dynamic reconfigurability. We particularly encourage submissions which focus on the mapping of algorithms and applications to heterogeneous FPGA-based systems as well as the overall impact of such architectures on the compute capacity, cost, power efficiency, and overall computational capabilities of data centers and supercomputers. Submissions may report on theoretical or applied research, implementation case studies, benchmarks, standards, or any other area that promises to make a significant contribution to our understanding of heterogeneous high-performance reconfigurable computing and will help to shape future research and implementations in this domain.
A non-comprehensive list of potential topics of interest:
1. FPGAs in Supercomputer, Cloud and Data Center: FPGAs in relation to challenges to Cloud/Data Center/Supercomputing posed by the end of Dennard scaling
2. Supercomputing, Cloud and Data Center Applications: Exploiting FPGA compute fabric to implement critical cloud/HPC applications
3. Leveraging Reconfigurability: Using reconfigurability for new approaches to algorithms used in cloud/HPC applications
4. Benchmarks: Compute performance and/or power and cost efficiency for cloud/HPC with heterogeneous architectures using FPGAs
5. Implementation Studies: Heterogenous Hardware and Management Infrastructure
6. Programming Languages/Runtimes/OS/Tools/Frameworks for Heterogeneous High Performance Reconfigurable Computing
7. Future-gazing: New Applications/The Cloud Enabled by Heterogeneous High Performance Reconfigurable Computing, Evolution of Computer Architecture in relation to Heterogeneous High Performance Reconfigurable Computing
8. Community building: Standards, consortium activity, open source, education, initiatives to enable and grow Heterogeneous High Performance Reconfigurable Computing
Prospective authors are invited to submit original and unpublished contributions as a ONE PAGE EXTENDED ABSTRACT in ACM SIG Proceedings format.
Michaela Blott, Xilinx
Franck Cappello, Argonne National Lab
Torsten Hoefler, ETH Zurich
Jason D. Bakos, University of South Carolina
Rizwan Ashraf, Oak Ridge National Laboratory
Paul Chow, University of Toronto
Carl Ebeling, Altera
Hans Eberle, NVIDIA
Alan George, University of Florida
Christoph Hagleitner, IBM
Miriam Leeser, Northeastern University
Viktor Prasanna, Univ. of Southern California
Marco Santambrogio, Politecnico Di Milano
Jeffrey Vetter, Oak Ridge National Lab