Call for Papers:

Workshop on Heterogeneous High-performance Reconfigurable Computing

Abstract or Paper Registration Deadline
August 15, 2019
Final Submission Deadline
August 15, 2019

Fifth International Workshop on Heterogeneous High-performance Reconfigurable Computing (H^2RC 2019)
in conjunction with Supercomputing 2019
in cooperation with the IEEE Technical Consortium on High Performance Computing (TCHPC)
Denver, Colorado, USA
November 17, 2019

Submission Deadline: August 15, 2019 (4- and 8- page papers)

Accepted 8-page manuscripts published/archived by IEEE (See below for descriptions of submission tracks.)

As conventional von-Neumann architectures are suffering from rising power densities, we are facing an era with power, energy efficiency, and cooling as first-class constraints for scalable HPC. FPGAs can tailor the hardware to the application, avoiding overheads and achieving higher hardware efficiency than general-purpose architectures. Leading FPGA manufacturers have recently made a concerted effort to provide a range of higher-level, easier-to-use high-level programming models for FPGAs, and much of the work in FPGA-based deep learning is built on these frameworks.

Such initiatives are already stimulating new interest within the HPC community around the potential advantages of FPGAs over other architectures. With this in mind, this workshop, now in its fifth year, brings together HPC and heterogeneous-computing researchers to demonstrate and share experiences on how newly-available high-level programming models, including OpenCL, are already empowering HPC software developers to directly leverage FPGAs, and to identify future opportunities and needs for research in this

Submissions are solicited for two tracks:
Track 1: Full-length papers (8 pages) for 25-minute oral presentation and publication in proceedings archived by IEEE.
Track 2: Extended abstracts (4 pages) for 15-minute oral presentation without publication.

Track 1 is targeted for technical papers containing a high level of implementation detail and analysis discussion of experimental results. Track 1 is suited for members of the academic and national lab community who prefer to have their work peer-reviewed, indexed and archived by IEEE.

Track 2 is targeted for industrial contributions that describe new capabilities and opportunities offered by emerging technologies and products or work in progress presentations by the academic and national lab community. The emphasis of this track is to initiate a discussion with the audience.

All submissions are reviewed and evaluated by at least three members of our technical program committee. From the TPC evaluation of each submission, the organizing committee will select papers for presentation based on a criteria that is equally weighted between scientific merit and level of interest and relevance to the HPC community.

1. Improvement of performance or efficiency of HPC or data center
applications with FPGAs
2. System integration of FPGAs in clouds and HPC systems
3. Leveraging reconfigurability
4. Benchmarks
6. Programming languages, tools, and frameworks
7. Future-gazing

Submission Deadline: August 15, 2019
Acceptance Notification: September 15, 2019
Camera-ready Manuscripts Due: October 11, 2019
Workshop Date: November 17, 2019

Jason D. Bakos, University of South Carolina
Michaela Blott, Xilinx
Franck Cappello, Argonne National Lab
Torsten Hoefler, ETH Zurich
Christian Plessl, Paderborn University, Germany

Technical Program Committee:
David Andrews, University of Arkansas
Rizwan Ashraf , Oak Ridge National Laboratory
Paul Chow, University of Toronto
Hans Eberle, Nvidia
Ken Eguro, Microsoft Research
Xin Fang, Northeastern University
Alan George, University of Pittsburgh
Christoph Hagleitner, IBM
Martin Herbordt, Boston University
Zheming Jin, Argonne National Laboratory
Andreas Koch, TU Darmstadt
Miriam Leeser, Northeastern University
Tiffany Mintz, Oak Ridge National Laboratory
Viktor Prasanna, University of Southern California
Yaman Umuroglu, Xilinx Research