Call for Papers:

Workshop on Languages, Tools, and Techniques for Accelerator Design

Final Submission Deadline
January 25, 2022

Second workshop on Languages, Tools, and Techniques for Accelerator Design. Co-located with ASPLOS ’22.

Motivation. Hardware acceleration is a key part of combating the stagnation of hardware performance scaling. Implementing accelerators with state-of-the-art hardware design flows, such as traditional HDLs and current HLS tools, remains a specialized task requiring EE training, proprietary toolchains, and extremely slow compile-edit-run cycles. While traditional approaches might be appropriate for developing general-purpose CPUs that will ship millions of units, they are an impediment to popularizing acceleration for the “long tail” of applications that could benefit from special-purpose hardware. With new language designs and new techniques inspired by traditional compilers research, there is an opportunity to turn accelerator construction from a years-long enterprise into a weekend project.

Scope. LATTE is a venue for discussion, debate, and brainstorming at the intersection of hardware acceleration and programming languages research. The focus is on new languages and tools that aim to let domain specialists, not just hardware experts, produce efficient accelerators. A full range of targets are in scope: ASICs (silicon), FPGAs, CGRAs, or future reconfigurable hardware. A wide variety of research topics are in scope including, but not limited to:

  • Domain-specific languages for accelerator design
  • Compilers for optimizing hardware designs
  • Verification, testing, and debugging techniques
  • Virtualization schemes for specialized & reconfigurable hardware

LATTE solicits two-page position papers that need not fit the mold of a traditional publication:

  • Early, in-progress research snapshots
  • Experience reports on building or deploying accelerators and the tools involved
  • Essays advocating for or against a general approach
  • Retrospectives on past efforts on tools, languages, and techniques for accelerator design
  • Calls for solutions to open challenges in the area (questions without answers)
  • Demonstrations of real systems (to be shown off in a live demo at the workshop)