Call for Papers:

Workshop on Performance Portable Programming Models for Accelerators

Final Submission Deadline
April 3, 2017

2nd International Workshop on Performance Portable Programming Models for Accelerators (P^3MA)
co-located with ISC 2017
Frankfurt, Germany
June 22, 2017

Paper Submission Deadline: April 3, 2017
Paper Acceptance Notification: May 14, 2017
Camera Ready Paper: June 3, 2017

High-level programming models aim to provide scientific applications a path onto HPC platforms with minimal loss of portability or programmer productivity. For example, using directives, developers can incrementally port their codes to heterogeneous systems with minimal code changes. Other emerging approaches include Domain Specific Languages (DSLs), C++ metaprogramming, and runtime APIs. Although these approaches attempt to introduce abstraction without performance penalty, programming challenges remain, with their designs, implementations, and ease-of-use on rapidly evolving hardware and diverse memory subsystems.

Programming approaches to address these concerns are continuously being developed within standards committees for C++, OpenCL, OpenMP, OpenACC, and various DSLs. This workshop is designed to assess improved features of programming models (including but not limited to directives-based and C++ library-based programming models), their implementations, and experiences with their deployment in HPC applications. The workshop provides a forum bringing together researchers and developers to examine heterogeneous computing and how it has been evolving across an increasingly diverse set of accelerated architectures. Including an invited opening keynote address and a closing Q&A panel with all presenters, this workshop will provide perspectives from current research and a chance for attendees to actively participate in this quickly changing and growing area of HPC research.

Topics of interest for workshop submissions include (but are not limited to):
– Experience porting applications using high-level models focused on performance portability and productivity
– Hybrid heterogeneous or many-core programming with models such as threading, message passing, and PGAS
– Asynchronous task and event driven APIs and execution/scheduling
– Performance-portable scientific libraries for heterogeneous systems
– Experiences in implementing compilers for performance portable programming on current and emerging architectures
– Low level communications APIs or runtimes that support accelerator architectures
– Extensions to programming models needed to support multiple memory hierarchies and accelerators
– Performance modeling and evaluation tools
– Power/energy studies
– Auto-tuning or optimization strategies
– Benchmarks and validation suites

We only accept paper submissions which are formatted correctly in LNCS style (single column format) using either the LaTeX document class or Word template. For details on the author guidelines, please refer to Springer’s website. Incorrectly formatted papers will be excluded from the reviewing process. Papers submissions are required to be within 18 pages in the above mentioned LNCS style. This includes all figures and references.

The submissions are “single-blind”, i.e. submissions are allowed to include the author names. All submitted manuscripts will be reviewed. The review process is not double blind, i.e., authors will be known to reviewers. Submissions will be judged on correctness, originality, technical strength, significance, quality of presentation, and interest and relevance to the conference scope. Submitted papers may NOT have appeared in or be under consideration for another conference, workshop or journal. Submissions should be made via EasyChair

Steering Committee:
Matthias Muller, RWTH Aachen University, Germany
Barbara Chapman, Stony Brook University, USA
Oscar Hernandez, ORNL, USA
Duncan Poole, OpenACC,
Torsten Hoefler, ETH, Zurich
Michael Wong, Codeplay Software Ltd, Canada
Mitsuhisa Sato, University of Tsukuba, Japan
Michael Klemm, OpenMP

Program Co-Chairs:
Sunita Chandrasekaran, University of Delaware, USA <>
Graham Lopez, ORNL, USA<>

Program Committee:
Samuel Thibault, INRIA, University of Bordeaux, France
James Beyer, NVIDIA, USA
Wei Ding, AMD, USA
Saber Feki, King Abdullah University, Saudi Arabia
Robert Henschel, Indiana University, USA
Eric Stotzer, Texas Instruments, USA
Amit Amritkar, University of Houston, USA
Guido Juckeland, HZDR, Germany
Will Sawyer, ETH, Zurich
Sameer Shende, University of Oregon, USA
Costas Bekas, IBM, Zurich
Toni Collis, University of Edinburgh, Scotland
Adrian Jackson, University of Edinburgh, Scotland
Henri Jin, NASA, USA
Andreas Knuepfer, TU Dresden, Germany
Steven Olivier, Sandia National Laboratory, USA
Suraj Prabhakaran, TU Darmstadt, Germany
Bora Ucar, ENS De Lyon, France
Veronica Vergara Larrea, ORNL, USA
Manisha Gajbe, Intel, USA