Call for Participation:

HPCA 2019

Early Registration Deadline
January 15, 2019
Registration Deadline
February 20, 2019

2019 IEEE International Symposium on High-Performance Computer Architecture (HPCA)
Washington D.C., USA
February 16-20, 2019

Early registration deadline: Jan 15, 2019
Please check the Registration Page:

The 25th International Symposium on High-Performance Computer Architecture provides a high-quality forum for scientists and engineers to present their latest research findings in this rapidly-changing field.

HPCA-25 will be held at Marriott Marquis Washington, D.C., in conjunction with the 24th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP-2019), the 17th International Symposium on Code Generation and Optimization (CGO-2019) and the 10th International Conference on Compiler Construction (CC-2019).

Feb. 18 (Monday): Srini Devadas, MIT, “Towards Secure High-Performance Computer Architectures”
Feb. 19 (Tuesday): Karin Strauss, Microsoft Research
Feb. 20 (Wednesday): Michael O’Boyle, University of Edinburgh, “Rethinking Compilation in a Heterogeneous World”

Workshops & Tutorials will take place on Saturday and Sunday from Feb. 16 to Feb. 17. Please note that workshops/tutorials are not included with the main conference registration. If you would like to attend the workshops/tutorials, but are not attending the general conference, please select the appropriate “Workshop/Tutorials” option only during the registration process.

Workshop Information
– The 5th Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era (HiPINEB 2019)
– The 2nd workshop on Energy Efficient Machine Learning and Cognitive Computing for Embedded Applications(EMC2-2019)
– The 2nd Workshop on Accelerators Architecture for Computational Biology and Bioinformatics (AACBB-2019)
– The 1st Workshop on Heterogeneous Computation in Specific Domain Accelerations (HCSDA-2019)
– The 1st Young Architect Workshop (YArch-2019)
– Built-in Security: Architecture, Chip and System (SecArch-2019)
– Workshop on Architectures and Systems for Autonomous Devices (ASAD-2019)

Tutorial Information
– FPGA-based Accelerated Cloud Computing with SDAccel
– MAERI-Enabling Rapid Design Space Exploration and Prototyping of DNN Accelerators
– BigDataBench: A Scalable and Unified Big Data and AI Benchmark Suite
– Device, Circuit, and Architecture Challenges for Super Conducting Chips
– Principles of Secure Processor Architecture Design

Please check the session information page.

Technical Sponsors: IEEE
Industry Sponsors: IMO Ventures, Huawei, Bitmain, Intel, AMD, Qualcomm,
Facebook, IBM, Microsoft, Alibaba, VMWare

General Co-chairs:
Ahmed Louri (GWU)
Guru Prasadh Venkataramani (GWU)

Program Co-chairs:
Rajeev Balasubramonian (Utah)
Vijayalakshmi Srinivasan (IBM Corp.)