March 3, 2021
IEEE International Symposium on High-Performance Computer Architecture 2021 (HPCA 2021)
Held online, February 27 – March 3, 2021
EARLY REGISTRATION OPENS: Jan 10, 2021
Please check the Registration Page.
The 27th International Symposium on High-Performance Computer Architecture provides a high-quality forum for scientists and engineers to present their latest research findings in this rapidly-changing field.
HPCA-27, initially planned in Seoul, South Korea, will be held virtually this year, in conjunction with the 26th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP-2021), the 19th International Symposium on Code Generation and Optimization (CGO-2021) and the 12th International Conference on Compiler Construction (CC-2021).
 Keynote Addresses
Title: A Journey to a Commercial-Grade Function-In-Memory (FIM) Chip Development
Abstract: —Emerging applications demand high off-chip memory bandwidth, but it becomes very expensive to further increase the bandwidth of off-chip memory under stringent physical constraints of chip packages and system boards. Besides, energy efficiency of moving data across the memory hierarchy of processors has steadily worsened with the stagnant technology scaling and poor data reuse characteristics of the emerging applications. To cost-effectively increase the bandwidth and energy efficiency, researchers began to reconsider the past processing-in-memory (PIM) architectures and advance them further, especially with recent integration technologies such as 2.5D/3D stacking. Albeit the recent advances, no major memory manufacturer had developed even a proof-of-concept silicon yet, not to mention a product. In this talk, I will start with discussing various practical and technical challenges that have been overlooked by researchers and prevented the industry from successfully commercializing PIM. Elegantly tackling the challenges, I first coined a concept of FIM as an alternative to PIM. Subsequently, I led the development of a commercial-grade FIM chip, which was fabricated by a major DRAM manufacturer for the first time and successfully integrated with unmodified commercial processors. I will present this journey in this talk.
Bio: Nam Sung Kim is a Senior Vice President at Samsung Electronics as well as a Professor at the University of Illinois. At Samsung he led the architecture definitions and designs of next generation DRAM devices including HBM, LPDDR, DDR, and GDDR. He has published more than 200 refereed articles to highly-selective conferences and journals in the field of circuit, architecture, and computer-aided design. For his contributions to developing power-efficient computer architectures, he was elevated to IEEE and ACM Fellows in 2016 and 2021, respectively, and received the ACM SIGARCH/IEEE-CS TCCA Influential ISCA Paper Award in 2017. He is also a hall of fame member of all three major computer architecture conferences, ISCA, MICRO, and HPCA.
 Workshop & Tutorials
Workshop & Tutorials will take place on Saturday and Sunday from Feb. 27 to Feb. 28. Please note that workshops/tutorials are not included with the main conference registration. If you would like to attend the workshops/tutorials, but are not attending the general conference, please select the appropriate “Workshop/Tutorials” option only during the registration process.
Workshop (W) & Tutorial (T) Information – February 27
– (T) A Deep Dive into Deep Learning Benchmarking and Analysis
– (T) Developing HPC accelerators using Xilinx FPGAs
– (W) The 2nd Championship Value Prediction
Workshop Information – February 28
– The Fifth Workshop on Cognitive Architectures (CogArch)
– Third Annual Workshop on Domain Specific System Architecture (DoSSA-3)
 Technical Sessions
Please check the session information page.
Official web site: https://hpca-conf.org/2021/
Technical Sponsors: IEEE
Industry Sponsors: Microsoft, ARM, Facebook
Facebook, IBM, Microsoft, Alibaba, VMWare
Jung Ho Ahn (Seoul National University) & John Kim (KAIST)
Murali Annavaram (University of Southern California)