Call for Participation:

ISCA 2014

Early Registration Deadline
May 24, 2014

Submitted by Natalie Enright Jerger
Early Registration Deadline Extended to May 24, 2014!


ISCA 2014
The 41st International Symposium on Computer Architecture

Minneapolis, MN — June 14-18, 2014


*** HOTEL CUT-OFF DATE: May 24, 2014

Saturday, June 14, 2014
T1: ESESC, a fast Multicore Simulator with Power and Thermal Models
T2: Analyzing Analytics (morning)
T3: Accelerating Big Data Processing with Hadoop and Memcached on
Datacenters with Modern Networking and Storage Architecture (afternoon)
T4: Architectural Modeling for Emerging Memory Technologies (afternoon)

Sunday, June 15, 2014
T5: Heterogeneous System Architecture (HSA): Architecture and Algorithms
T6: Research Infrastructures for Accelerator-centric Architectures
T7: PinPoints: Simulation Region Selection with PinPlay and Sniper (morning)
T8: Graphics Processor Unit (GPU) Programming Support in Open Computer
Vision (OpenCV) Applications (afternoon)

Saturday, June 14, 2014
W1: 2nd International Workshop on Parallelism in Mobile Platforms (PRISM-2)
W2: 2nd Workshop on Near-threshold Computing (WNTC)
W3: Heterogeneous Architectures: Software and Hardware (HASH) (CANCELLED)
W4: 1st Workshop on Neuromorphic Architectures (NeuroArch)
W5: Memory Forum (afternoon)

Sunday, June 15, 2014
W6: 3rd Workshop on Hardware and Architectural Support for Security
and Privacy (HASP)
W7: 2nd Workshop on Many-core Embedded Systems (MES)
W8: 4th Workshop on Energy Secure System Architectures (ESSA)
W9: 4th Workshop on Architectures and Systems for Big Data (ASBD 2014)
W10: Championship Branch Prediction (CBP-4) (morning)
W11: 11th Workshop on Duplicating, Deconstructing and Debunking (WDDD)
W12: 7th Annual Workshop on Architectural and Microarchitectural
Support for Binary Translation (AMAS-BT) (afternoon)

Monday, June 16, 2014

Monday, 8:45am-9:45am
Keynote I: Insight into the MICROSOFT XBOX ONE Technology
Dr. Ilan Spillinger, Corporate Vice President, Technology and Silicon,

Monday, 10:45am-12:00pm
Session 1: Machines and Prototypes

Unifying on-chip and inter-node switching within the Anton 2 network
Brian Towles, J.P. Grossman, Brian Greskamp, and David E. Shaw (D. E.
Shaw Research)

A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services
Andrew Putnam (Microsoft), Adrian M. Caulfield (Microsoft), Eric S.
Chung (Microsoft), Derek Chiou (Microsoft and University of Texas at
Austin), Kypros Constantinides (Amazon), John Demme (Columbia
University), Hadi Esmaeilzadeh (Georgia Institute of Technology),
Jeremy Fowers (Microsoft), Gopi Prashanth Gopal (Microsoft), Jan Gray
(Microsoft), Michael Haselman (Microsoft), Scott Hauck (Microsoft and
University of Washington), Stephen Heil (Microsoft), Amir Hormati
(Google), Joo-Young Kim (Microsoft), Sitaram Lanka (Microsoft), James
Larus (EPFL), Eric Peterson (Microsoft), Simon Pope (Microsoft), Aaron
Smith (Microsoft), Jason Thong (Microsoft), Phillip Yi Xiao
(Microsoft), Doug Burger (Microsoft)

SCORPIO: A 36-Core Research Chip Demonstrating Snoopy Coherence on a
Scalable Mesh NoC with In-Network Ordering
Bhavya K. Daya, Chia-Hsin Owen Chen, Suvinay Subramanian, Woo-Cheol
Kwon, Sunghyun Park, Tushar Krishna, Jim Holt, Anantha P.
Chandrakasan, Li-Shiuan Peh (Massachusetts Institute of Technology)

Monday, 1:15pm-2:55pm
Section 2A: Resilience

Avoiding Core’s DUE & SDC via Acoustic Wave Detectors and Tailored
Error Containment and Recovery
Gaurang Upasani (Universitat Politècnica de Catalunya), Xavier Vera
(Intel Barcelona Research Center), Antonio González (Universitat
Politècnica de Catalunya / Intel Barcelona Research Center)

MemGuard: A Low Cost and Energy Efficient Design to Support and
Enhance Memory System Reliability
Long Chen, Zhao Zhang (Iowa State University)

GangES: Gang Error Simulation for Hardware Resiliency Evaluation
Siva Kumar Sastry Hari (NVIDIA), Radha Venkatagiri (University of
Illinois at Urbana-Champaign), Sarita V. Adve (University of Illinois
at Urbana-Champaign), Helia Naeimi (Intel Labs)

Real-World Design and Evaluation of Compiler-Managed GPU Redundant
Jack Wadden (University of Virginia), Alexander Lyashevsky (AMD
Research), Sudhanva Gurumurthi (AMD Research), Vilas Sridharan (RAS
Architecture, AMD), Kevin Skadron (University of Virginia)

Section 2B: Design Space Exploration

ArchRanker: A Ranking Approach to Design Space Exploration
Tianshi Chen (Chinese Academy of Sciences), Qi Guo (Carnegie Mellon
University), Ke Tang (University of Science and Technology of China),
Olivier Temam (Inria), Zhiwei Xu (Chinese Academy of Sciences),
Zhi-Hua Zhou (Nanjing University), Yunji Chen (Chinese Academy of

Aladdin: A Pre-RTL, Power-Performance Accelerator Simulator Enabling
Large Design Space Exploration of Customized Architectures
Yakun Sophia Shao, Brandon Reagen, Gu-Yeon Wei, David Brooks (Harvard

SynFull: Synthetic Traffic Models Capturing Cache Coherent Behaviour
Mario Badr, Natalie Enright Jerger (University of Toronto)

Harnessing ISA Diversity: Design of a Heterogeneous-ISA Chip Multiprocessor
Ashish Venkat, Dean M. Tullsen (University of California, San Diego)

Monday, 3:25pm-5:05pm
Section 3A: Caches

The Direct-to-Data (D2D) Cache: Navigating the Cache Hierarchy with a
Single Lookup
Andreas Sembrant, Erik Hagersten, David Black-Schaffer (Uppsala University)

SC2: A Statistical Compression Cache Scheme
Angelos Arelakis, Per Stenstrom (Chalmers University of Technology)

The Dirty-Block Index
Vivek Seshadri (Carnegie Mellon University), Abhishek Bhowmick
(Carnegie Mellon University), Onur Mutlu (Carnegie Mellon University),
Phillip B. Gibbons (Intel Pittsburgh), Michael A. Kozuch (Intel
Pittsburgh), Todd C. Mowry (Carnegie Mellon University)

Going Vertical in Memory Management: Handling Multiplicity by Multi-policy
Lei Liu (Chinese Academy of Sciences), Yong Li (University of
Pittsburgh), Zehan Cui (Chinese Academy of Sciences), Yungang Bao
(Chinese Academy of Sciences), Mingyu Chen (Chinese Academy of
Sciences), Chengyong Wu (Chinese Academy of Sciences)

Section 3B: GPUs and Parallelism

Fine-grain Task Aggregation and Coordination on GPUs
Marc S. Orr (University of Wisconsin-Madison / AMD Research), Bradford
M. Beckmann (AMD Research), Steven K. Reinhardt (AMD Research), David
A. Wood (University of Wisconsin-Madison / AMD Research)

Enabling Preemptive Multiprogramming on GPUs
Ivan Tanasic (Barcelona Supercomputing Center / Universitat
Politecnica de Catalunya), Isaac Gelado (NVIDIA Research), Javier
Cabezas (Barcelona Supercomputing Center / Universitat Politecnica de
Catalunya), Alex Ramirez (Barcelona Supercomputing Center /
Universitat Politecnica de Catalunya), Nacho Navarro (Barcelona
Supercomputing Center / Universitat Politecnica de Catalunya), Mateo
Valero (Barcelona Supercomputing Center / Universitat Politecnica de

Single-Graph Multiple Flows: Energy Efficient Design Alternative for GPGPUs
Dani Voitsechov, Yoav Etsion (Technion ? Israel Institute of Technology)

HELIX-RC: An Architecture-Compiler Co-Design for Automatic
Parallelization of Irregular Programs
Simone Campanoni (Harvard University), Kevin Brownell (Harvard
University), Svilen Kanev (Harvard University), Timothy M. Jones
(University of Cambridge), Gu-Yeon Wei (Harvard University), David
Brooks (Harvard University)

Tuesday, June 17, 2014

Tuesday, 8:30-9:30
Keynote II: Should Computer Architects Take a Closer Look At Today’s
Most Pervasive Computer System ? The Mobile Phone?
Prof. Trevor Mudge, Department of Computer Science and Engineering,
University of Michigan

Tuesday, 10:45am-12:00pm
Section 4: Emerging Technologies

Efficient Digital Neurons for Large Scale Cortical Architectures
James E. Smith (University of Wisconsin-Madison)

An Examination of the Architecture and System-level Tradeoffs of
Employing Steep Slope Devices in 3D CMPs
Karthik Swaminathan, Huichu Liu, Jack Sampson, Vijaykrishnan Narayanan
(Pennsylvania State University)

STAG: Spintronic-Tape Architecture for GPGPU Cache Hierarchies
Rangharajan Venkatesan, Shankar Ganesh Ramasubramanium, Swagath
Venkataramani, Kaushik Roy, Anand Raghunathan (Purdue University)

Tuesday, 2:00pm-3:15pm
Section 5A: NVRAM

Memory Persistency
Steven Pelley, Peter M. Chen, Thomas F. Wenisch (University of Michigan)

Reducing Access Latency of MLC PCMs through Line Striping
Morteza Hoseinzadeh (Sharif University of Technology), Mohammad
Arjomand (Sharif University of Technology), Hamid Sarbazi-Azad (Sharif
University of Technology / Institute for Research in Fundamental

HIOS: A Host Interface I/O Scheduler for Solid State Disks
Myoungsoo Jung (University of Texas at Dallas), Wonil Choi (University
of Texas at Dallas), Shekhar Srikantaiah (Qualcomm), Joonhyuk Yoo
(Daegu University), Mahmut T. Kandemir (Pennsylvania State University)

Section 5B: Datacenters and Cloud

Towards Energy Proportionality for Large-Scale Latency-Critical Workloads
David Lo (Stanford University), Liqun Cheng (Google), Rama Govindaraju
(Google), Luiz André Barroso (Google), Christos Kozyrakis (Stanford

SleepScale: Runtime Joint Speed Scaling and Sleep States Management
for Power Efficient Data Centers
Yanpei Liu (University of Wisconsin-Madison), Stark C. Draper
(University of Toronto), Nam Sung Kim (University of Wisconsin-Madison)

Optimizing Virtual Machine Consolidation Performance on NUMA Server
Architecture for Cloud Workloads
Ming Liu, Tao Li (University of Florida)

Tuesday, 3:45pm-5:00pm
Section 6A: DRAM

Row-Buffer Decoupling: A Case for Low-Latency DRAM Microarchitecture
Seongil O (Seoul National University), Young Hoon Son (Seoul National
University), Nam Sung Kim (University of Wisconsin-Madison), Jung Ho
Ahn (Seoul National University)

Half-DRAM: a High-bandwidth and Low-power DRAM Architecture from the
Rethinking of Fine-grained Activation
Tao Zhang (Pennsylvania State University / NVIDIA), Ke Chen (Oracle),
Cong Xu (Pennsylvania State University), Guangyu Sun (Peking
University), Tao Wang (Peking University), Yuan Xie (Pennsylvania
State University)

Flipping Bits in Memory Without Accessing Them: An Experimental Study
of DRAM Disturbance Errors
Yoongu Kim (Carnegie Mellon University), Ross Daly, Jeremie Kim
(Carnegie Mellon University), Chris Fallin, Ji Hye Lee (Carnegie
Mellon University), Donghyuk Lee (Carnegie Mellon University), Chris
Wilkerson (Intel Labs), Konrad Lai, Onur Mutlu (Carnegie Mellon

Section 6B: Circuits and Architecture

Architecture Implications of Pads as a Scarce Resource
Runjie Zhang (University of Virginia), Ke Wang (University of
Virginia), Brett H. Meyer (McGill University), Mircea R. Stan
(University of Virginia), Kevin Skadron (University of Virginia)

Increasing Off-Chip Bandwidth in Multi-Core Processors with Switchable Pins
Shaoming Chen, Yue Hu, Ying Zhang, Lu Peng, Jesse Ardonne, Samuel
Irving, Ashok Srivastava (Louisiana State University)

A Low Power and Reliable Charge Pump Design for Phase Change Memories
Lei Jiang, Bo Zhao, Jun Yang, Youtao Zhang (University of Pittsburgh)

Wednesday, June 18, 2014

Wednesday, 8:30am-10:10am
Section 7A: Coherence and Replay

Fractal++: Closing the Performance Gap between Fractal and
Conventional Coherence
Gwendolyn Voskuilen, T. N. Vijaykumar (Purdue University)

OmniOrder: Directory-Based Conflict Serialization of Transactions
Xuehai Qian (University of California, Berkeley), Benjamin Sahelices
(Universidad de Valladolid), Josep Torrellas (University of Illinois
at Urbana-Champaign)

Pacifier: Record and Replay for Relaxed-Consistency Multiprocessors
with Distributed Directory Protocol
Xuehai Qian (University of California, Berkeley), Benjamin Sahelices
(Universidad de Valladolid), Depei Qian (Beihang University)

Replay Debugging: Leveraging Record and Replay for Program Debugging
Nima Honarmand, Josep Torrellas (University of Illinois at Urbana-Champaign)

Section 7B: Security/OOO Processors

The CHERI capability model: Revisiting RISC in an age of risk
Jonathan Woodruff (University of Cambridge), Robert N. M. Watson
(University of Cambridge), David Chisnall (University of Cambridge),
Simon W. Moore (University of Cambridge), Jonathan Anderson
(University of Cambridge), Brooks Davis (SRI International), Ben
Laurie (Google UK Ltd), Peter G. Neumann (SRI International), Robert
Norton (University of Cambridge), Michael Roe (University of Cambridge)

CODOMs: Protecting Software with Code-centric Memory Domains
Lluís Vilanova (Barcelona Supercomputing Center / Universitat
Politècnica de Catalunya / Technion ? Israel Institute of Technology),
Muli Ben-Yehuda (Technion – Israel Institute of Technology), Nacho
Navarro (Barcelona Supercomputing Center / Universitat Politècnica de
Catalunya), Yoav Etsion (Technion ? Israel Institute of Technology),
Mateo Valero (Barcelona Supercomputing Center / Universitat
Politècnica de Catalunya)

EOLE: Paving the Way for an Effective Implementation of Value Prediction
Arthur Perais, André Seznec (IRISA/INRIA)

Improving the Energy Efficiency of Big Cores
Kenneth Czechowski (Georgia Institute of Technology), Victor W. Lee
(Intel), Ed Grochowski (Intel), Ronny Ronen (Intel), Ronak Singhal
(Intel), Richard Vuduc (Georgia Institute of Technology), Pradeep
Dubey (Intel)

Wednesday, 10:40am-12:20pm
Section 8: Accelerators

General-Purpose Code Acceleration with Limited-Precision Analog Computation
Renée St. Amant (University of Texas at Austin), Amir Yazdanbakhsh
(Georgia Institute of Technology), Jongse Park (Georgia Institute of
Technology), Bradley Thwaites (Georgia Institute of Technology), Hadi
Esmaeilzadeh (Georgia Institute of Technology), Arjang Hassibi
(University of Texas at Austin), Luis Ceze (University of Washington),
Doug Burger (Microsoft Research)

Race Logic: A Hardware Acceleration for Dynamic Programming Algorithms
Advait Madhavan, Timothy Sherwood, Dmitri Strukov (University of
California, Santa Barbara)

Eliminating Redundant Fragment Shader Executions on a Mobile GPU via
Hardware Memoization
Jose-Maria Arnau (Universitat Politecnica de Catalunya), Joan-Manuel
Parcerisa (Universitat Politecnica de Catalunya), Polychronis
Xekalakis (Intel)

WebCore: Architectural Support for Mobile Web Browsing
Yuhao Zhu, Vijay Janapa Reddi (The University of Texas at Austin)

General Co-Chairs
Pen-Chung Yew, University of Minnesota
Antonia Zhai, University of Minnesota

Program Chair
Steve Keckler, NVIDIA/University of Texas at Austin

Workshop Co-Chairs
David Wentzlaff, Princeton University
Nuwan Jayasena, AMD Research

Tutorial Co-Chairs
Martha Kim, Columbia University
Debbie Marr, Intel

Finance Chair
Yuan Xie, Pennsylvania State University

Industry Liaison Co-Chairs
Hyesoon Kim, Georgia Institute of Technology
Samantika Subramaniam, Intel

Local Arrangements Chair
John Sartori, University of Minnesota

Web Chair
Omer Khan, University of Connecticut

Publicity Co-Chairs
Chia-Lin Yang, National Taiwan University
Natalie Enright Jerger, University of Toronto
Lieven Eeckhout, Ghent University

Registration Chair
Ulya Karpuzcu, University of Minnesota

Proceedings Chair
Eric Chung, Microsoft Research

Travel Award Chair
James Tuck, NC State University

Submission Chair
Paul Gratz, Texas A&M University

Steering Committee
Mark Horowitz, Stanford University
David Kaeli, Northeastern University
Shih-Lien Lu, Intel
Avi Mendelson, Technion
Margaret Martonosi, Princeton University
Yale Patt, University of Texas at Austin
Josep Torrellas, University of Illinois at Urbana-Champaign
David A. Wood, University of Wisconsin-Madison