Call for Participation:

NoCArc 2020 (Global Online Event, October 18, 2020)

Early Registration Deadline
October 16, 2020

NoCArc 2020
IEEE/ACM 13th International Workshop on Network on Chip Architectures. (
To be held in conjunction with the 53rd Annual IEEE/ACM International Symposium on Microarchitecture®
October 18, 2020, Global Online Event

Registration Information

Registration allows full access to all the live events (all keynotes, regular paper sessions, live workshops/tutorials, and recordings) that are made as part of MICRO.
Early registration ends on Friday, October 16, at 11:59 PM PDT. Very low registration fees to maximize global participation.
Registration Link:

General Information

It is well recognized that on-chip communication plays a dominant role in determining the overall performance, reliability, and energy figures in many-core architectures. Today, virtually all large-scale chips are designed on the basis of the Network-on-Chip (NoC). NoCs are now part of a large number of products that we use every day and this is a proof that NoC paradigm is scalable and can be adapted to support various computational paradigms, ranging from multiprocessing to reconfigurable computing and the emerging area of neuromorphic computing. The goal of NoCArc workshop is to provide a forum for researchers to present and discuss innovative ideas and solutions related to the design and implementation of many-core architectures based on the NoC paradigm.


* Exciting keynote talks (
– “How to Evaluate Efficient Deep Neural Network Approaches” delivered by Vivienne Sze, Associate Professor of Electrical Engineering and Computer Science, MIT, USA. (
– “Architecting Chiplet-based Systems” delivered by Natalie Enright Jerger, Professor of Electrical and Computer Engineering at the University of Toronto, Canada. (

* Panel discussion on “Unconventional computing and what it means for the future of interconnects” (
– Marc Riedel, University of Minnesota [DNA Computing]
– Sudeep Pasricha, Colorado State University [Photonic Interconnects]
– Abu Sebastian, IBM Zurich [Processing in Memory]
– Rajeev Balasubramonian, University of Utah [Processing in Memory]
– Masoud Babaie, TU Delft [Quantum Computing]
– Baris Taskin, Drexel University [Wireless Interconnects]

* Technical paper presentation and Q&A on
– Run-time Reconfiguration of NoC in Xilinx ACAP Architecture
– Predicting Local Congestion at Fine-grain Levels in Networks-on-Chip Using Spiking Neural Networks
– Min/max time limits and energy penalty of communication scheduling in ring-based ONoC
– Two-Phase High-Throughput Synthesizable Synchronization FIFOs for Mixed-Timing NoCs
– Evaluation of Performance in AUTOSAR Micro-ECUs using dedicated System Cores on a Multi-Core Processor