Call for Participation:

PyMTL Tutorial

Early Registration Deadline
May 24, 2019

PyMTL Tutorial: A Next-Generation Python-Based Framework for Hardware Generation, Simulation, and Verification
in conjunction with ISCA 2019
Phoenix, Arizona, USA
June 22nd, 2019

The purpose of this tutorial is to introduce the computer architecture research community to the features and capabilities of the new version of PyMTL, a next-generation Python-based hardware generation, simulation, and verification framework.

* Why PyMTL?
Computer architecture researchers are increasingly exploring the hardware and software aspects of accelerator-centric architectures, and this has resulted in a trend towards implementing accelerators at the register-transfer level and even fabricating accelerator-centric test chips. However, the conventional wisdom is that designing, implementing, testing, and evaluating RTL accelerators is a complex, time-consuming, and frustrating process. These challenges in the computer architecture research community mirror the challenges faced by commercial, government, and hobbyist hardware designers. These challenges have motivated some design teams to augment or even replace traditional domain-specific hardware description languages (HDLs) with a mix of different high-level hardware generation, simulation, and verification frameworks. PyMTL is a next-generation Python-based framework that unifies hardware generation, simulation, and verification into a single environment. The Python language provides a flexible dynamic type system, object-oriented programming paradigms, powerful reflection and introspection, lightweight syntax, and rich standard libraries. PyMTL builds upon these productivity features to enable a designer to write more succinct descriptions, to avoid crossing any language boundaries for development, testing, and evaluation, and to use the complete expressive power of the host language for verification, debugging, instrumentation, and profiling. The hope is that PyMTL can reduce time-to-paper (or time-to-solution) by improving the productivity of design, implementation, verification, and evaluation.

* The PyMTL Workflow:
A typical workflow using PyMTL is shown above. The designer starts from developing a functional-level (FL) design-under-test (DUT) and test bench completely in Python. Then the DUT is iteratively refined to the cycle level (CL) and register-transfer level (RTL), along with verification and evaluation using Python-based simulation and the same test bench. The designer can then translate a PyMTL RTL model to Verilog and use the same test bench for co-simulation. Note that designers can also co-simulate existing SystemVerilog source code with a PyMTL test bench. The ability to simulate/co-simulate the design in the Python runtime environment drastically reduces the iterative development cycle, eliminates any semantic gap, and makes it feasible to adopt verification methodologies emerging in the open-source software community. Finally, the designer can push the translated DUT through an FPGA/ASIC toolflow and can even reuse the same PyMTL test bench during prototype bringup.

* The New Version of PyMTL:
This hands-on tutorial will introduce participants to the new version of PyMTL which is scheduled for a beta release in June. The new version of PyMTL maintains some of the best features of the current version including: support for highly paramterized chip generators; a unified framework for functional-, cycle-, and register-transfer level modeling; pure-Python-based simulation; elegant translation of PyMTL RTL to Verilog RTL; and first-class support for co-simulation of PyMTL and Verilog models through Python/Verilator integration. The new version of PyMTL will additionally include: a completely new execution model based on statically scheduled concurrent sequential update blocks; improved simulation performance; first-class support for method-based interfaces; PyMTL passes for analyzing, instrumenting, and transforming PyMTL models; and improved verification methodologies.

Our objective is to provide attendees with answers to the following questions:
– What kind of research problems can PyMTL help me solve?
– How do I build functional-level, cycle-level, and register-transfer-level models in PyMTL?
– How do I generate Verilog HDL from PyMTL RTL models and push them through an ASIC toolflow?
– How do I create flexible testing harnesses in PyMTL that work across abstraction levels?
– How do I incorporate PyMTL into my existing research flow?
– How do I use existing Verilog IP with PyMTL?

Christopher Batten, Cornell University
Shunning Jiang, Cornell University
Christopher Torng, Cornell University
Yanghui Ou, Cornell University
Peitian Pan, Cornell University