Call for Participation:

RISC-V Workshop and Bootcamp

Early Registration Deadline
January 1, 2015

Submitted by Krste Asanovic

1st RISC-V Workshop and Boot Camp

January 14-15, 2015
Monterey, CA, USA

RISC-V (pronounced “risk-5”) is a new instruction set architecture
(ISA) that was originally designed to support computer architecture
research and education, but which we now hope will become a standard
open architecture for industry implementations. RISC-V was originally
developed in the Computer Science Division of the EECS Department at
the University of California, Berkeley, but has been made freely
available open-source under the BSD license for anyone to use.

The goals of this workshop are to inform the community of recent
activity in the various RISC-V projects underway around the globe and
to build consensus on future steps in the RISC-V project, while the
bootcamp provides an opportunity to learn about the existing RISC-V
infrastructure from the RISC-V development team. The workshop and
bootcamp will feature demos of multiple RISC-V silicon tapeouts as
well as FPGA board designs and associated software tools.

Space will be limited, so please register early!

Early Bird registration ends December 1.