Call for Participation:

ROAD4NN: Workshop at DAC 2020

Registration Deadline
July 17, 2020

ROAD4NN 2020: Workshop on Research Open Automatic Design for Neural Networks 2020
DAC 2020 Full Day Workshop, Jul 19, 2020, 9am – 4pm Pacific Time
To be held virtually

Registration Deadline: July 17, 2020


In the past decade, machine learning, especially neural network based deep learning, has achieved an amazing success. Various neural networks (NNs), such as CNNs, RNNs, LSTMs and SNNs, have been deployed for various industrial applications like image classification, speech recognition, and automated control. On one hand, there is a very fast algorithm evolvement of neural network models, almost every week there is a new model from a major academic and/or industry institute. On the other hand, all major industry giants have been developing and/or deploying specialized hardware platforms to accelerate the performance and energy-efficiency of neural networks across the cloud and edge devices. This include Nvidia GPU, ARM Embedded CPUs, Qualcomm Adreno Embedded GPUs, Intel Nervana/Habana/Loihi ASICs, Intel and Xilinx FPGAs, Google TPU, Microsoft Brainwave, Amazon Inferentia, Huawei Da Vinci architecture, and Cambricon NPU, to name just a few. However, there is a significant gap between the fast algorithm evolvement and staggering hardware development.

In this workshop, we focus on the open research problems of automatic design for neural networks, where we discuss full stack open source infrastructure support to develop and deploy novel neural networks, including novel algorithms and applications, hardware architectures and emerging devices, hardware-software co-design, as well as programming, compiler, system, and tool support. We will bring together academic and industry experts to share their experience, discuss challenges they face as well as potential focus areas for the community.

There will be a keynote given by Prof. Deming Chen, UIUC, who also co-founded Inspirit IoT, Inc.; the keynote title is “Elegant and Effective Co-design of Machine-Learning Algorithms and Hardware Accelerators”. We have also invited 12 renowned researchers from academic and industry to give invited talks, who come from MIT, TAMU, UCSB, UC Berkeley, Cornell, Notre Dame, Rice, NCSU, W&M, Microsoft, and Xilinx. For free registration and more information on the workshop schedule, please visit:

Welcome to register and attend (it’s free)! We will send out the Zoom invitation to the registered attendees before the workshop event.