Call for Participation:

Tutorial for Learning and Using the Intel Xeon with Integrated FPGA

Early Registration Deadline
July 15, 2017
Registration Deadline
September 2, 2017

Intel Hardware Accelerator Research Program: A Tutorial for Learning and Using the Intel Xeon with Integrated FPGA
in conjunction with FPL’17
Ghent, Belgium
September 8, 2017

This full day tutorial will cover the architecture and programming model of the Intel© Xeon© with Integrated FPGA. This reconfigurable hardware has an integrated host processor with memory coherency between the Intel© Xeon© processor and the FPGA providing a heterogeneous compute solution for workload optimizations. With a simplified programming model (support for virtual addressing and data caching), the Intel Xeon with integrated FPGA enables new classes of algorithms for acceleration.

The tutorial will also highlight Intel’s Hardware Acceleration Research Program which provides faculty and researchers access to pre-production Intel© Xeon© with integrated FPGA systems and is spurring research in programming tools, operating systems, and innovative applications for accelerator-based computing systems.

During the session, the hardware and software architectures will be explained as well as how it can be programmed using RTL and OpenCL. A multi-hour hands-on lab session will be held to allow attendees to get first-hand experience.

List of Topics to be Covered:
– Intel© Xeon© with Integrated FPGA Hardware and Software Architecture Overview
– Accelerator Abstraction Layer Overview
– Core Cache Interface Overview and Accelerator Function Unit Design
– Memory Protocol Factory overview
– OpenCL Programming
– High Level Design (HLD) Methodology
– Hands-on Labs for RTL, HLD, and OpenCL

Pre-Requisite: basic knowledge of computer logic design and FPGA fundamentals.