Tutorial on OpenPiton and Ariane: The RISC-V Hardware Research Platform
in conjunction with ISCA 2019
Phoenix, Arizona, USA
June 23, 2019
OpenPiton+Ariane is a permissively-licensed open-source framework designed to enable scalable architecture research prototypes. With the recent addition of SMP Linux running on FPGA, OpenPiton+Ariane is the first Linux-booting, open-source, RISC-V system that scales from single-core to manycore. Building on the maturity of the OpenPiton platform and the Ariane 64-bit RISC-V processor, OpenPiton+Ariane is the ideal RISC-V hardware research platform.
On Sunday June 23rd at ISCA/FCRC 2019 we will be holding a half-day afternoon tutorial to get interested users acquainted with the platform. This is a hands-on session which will first introduce attendees to our validation infrastructure using open-source simulators. Attendees will also learn how to synthesise multiple cores to FPGA and get direct experience with booting multicore Linux on our provided FPGAs. We will also teach attendees how to configure and extend the OpenPiton architecture to enable architecture research.
Register for the tutorial and enjoy an early registration discount until May 24th (https://iscaconf.org/isca2019/registration.html). More details on our tutorial are available at http://parallel.princeton.edu/openpiton/ISCA19_tutorial.html