Call for Participation:

Workshop on Trends In Machine-Learning

Early Registration Deadline
May 21, 2017

Workshop on Trends In Machine-Learning: Perspective from ML Research and Industry
in conjunction with ISCA 2017
Toronto, Canada
June 25, 2017

Machine-Learning has now become a pervasive tool used throughout the industry. This trend, combined with the plateauing of Moore’s Law, has made hardware accelerators for machine-learning one of the promising paths forward.

The goal of this workshop is to help the architecture community understand where Machine-Learning is headed, so that researchers & engineers can appropriately plan and design their accelerators. Essentially, we want to kick off a two-way conversation between the Machine-Learning community and the Architecture community.

For that purpose, we have assembled a list of prestigious speakers (by invitation only) from the Machine-Learning domain, both from industry and academia.

Yoshua Bengio, Univ. Montreal (one of Deep Neural Nets “founding fathers”)
Eugenio Culurciello, Purdue Univ. (co-inventor of NeuFlow)
Bill Dally, NVIDIA (Chief Scientist and Senior Vice President of Research)
Ofer Dekel, MSR (Principal Researcher in the Machine Learning and Optimization group)
Greg Diamos, Baidu (Senior Research Scientist in Baidu Silicon Valley AI Lab)
Ali Farhadi, Univ. Washington & AI2, (Professor & Senior Research Manager, Allan Institute for Artificial Intelligence – AI2)
Yangqing Jia, Facebook (Author of Caffe, and Lead of large-scale platform for AI at Facebook)
Carey K. Kloss, Intel (Sr. Director, was VP of Hardware Engineering at Nervana)
Scott Legrand, Teza (formerly Amazon) (Led DSSTNE, Amazon framework for sparse ML)
Jason Mars, (CEO and co-founder of
Ruchir Puri, IBM (Chief architect of IBM Watson ML System)
Tianqi Chen, author of MxNet (selected as AWS deep learning framework), Univ. Wisconsin
Vincent Vanhoucke, Google (Principal Scientist and Tech Lead in Brain)

Please register via the conference registration page.

Philosophy & Goals
The industry and the academic community have now fully embraced machine-learning as a major application domain, with many hardware solutions being explored by different companies (e.g., Nvidia, Intel, Microsoft, IBM or Google), and academic groups.

With the advent of custom accelerators, the organization of hardware research is profoundly changing, with the need for hardware researchers and engineers to essentially become experts in the algorithmic field their hardware accelerators are targeting.

In a rapidly evolving domain like machine-learning, one of the key challenges for hardware researchers and engineers is to reconcile the longer timeline of hardware design with the fast algorithmic evolutions by understanding, anticipating, and later reflecting in their designs, future trends in machine-learning.

This is the first goal of this workshop: to help steer machine-learning accelerator designs towards the most important and foreseeable evolutions in machine-learning techniques, and to help hardware accelerator designers achieve the delicate balance between efficiency and flexibility.

The second goal of the workshop is to observe that machine-learning accelerators progress will plateau if hardware researchers and engineers passively try to support whatever algorithmic variation machine-learning is exploring. Customization has become a major scalability path, and a too high demand on generality will hamper the ability of hardware researchers and engineers to scale up the efficiency of their accelerators. So our goal is also to kick off a two-way conversation between the hardware and machine-learning communities on trends in machine-learning and their impact on hardware, and hopefully lead to co-design ideas.

Olivier Temam, Google
Luis Ceze, Univ. Washington (SIGARCH “visioning” workshops committee member)
Joel Emer, MIT and Nvidia (SIGARCH “visioning” workshops committee member)
Karin Strauss, Microsoft Research (SIGARCH “visioning” workshops committee member)