Tool Release: Argus – An End-to-End Framework for Accelerating CNNs on FPGAs

We are pleased to announce the release of the Argus online Verilog Code Generator tool. Argus is an end-to-end framework for accelerating CNNs on FPGAs. The core of Argus is an accelerator generator that translates high-level CNN descriptions into efficient multi-core accelerator designs. Argus explores an extensive design space, jointly optimizing all design aspects for the target FPGA and generating multi-core accelerator designs that achieve near-perfect dynamic arithmetic unit utilization.

Our online code generator allows anyone to use Argus to produce network-optimized and FPGA-optimized CNN accelerators in Verilog. To minimize user effort, Argus includes a model parser for importing CNN models from popular machine learning frameworks and a software stack for running an FPGA-backed CNN inference microservice.  The tool can be accessed online at

The Argus tool was built by researchers in the COMPAS Lab at Stony Brook University’s departments of Computer Science and Electrical and Computer Engineering. Argus is part of a larger research effort studying efficient hardware acceleration of machine learning.