10000 ft overview: This is a very intricate attack but the root cause is unflushed speculative state from the cache resulting in a timing variations.
Questions to ponder as the community considers the implications:
– Is this enough for processor vendors to consider microarchitectural timing attacks in their threat model?
– How are companies going to handle hardware 0-days? More frequent microcode patching? disabling/fuzzing timing sources to frustrate attackers? AV signatures for spy code? compiler fixes?
More here from last year on this topic:
HARDWARE 0-DAYS: PUBLISH, SELL OR HOARD? (PART I)
HARDWARE 0-DAYS: PUBLISH, SELL OR HOARD? (PART II)
HARDWARE 0-DAYS: PUBLISH, SELL OR HOARD? (PART III)
HARDWARE 0-DAYS: PUBLISH, SELL OR HOARD? (PART IV)
Offensive Security Research in Computer Architecture Conferences
About the Author: Simha Sethumadhavan is an associate professor in the Computer Science Department at Columbia University. His research interests are in computer architecture and computer security. He is @thesimha on twitter.
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