Archive of posts tagged: Security
Tug of War for Secure Caches: Randomization, Partitioning, or Both?
This blog post is a continuation of Gururaj’s SIGARCH blog, written three years ago. It revisits the design of secure caches and, primarily, two design choices available to the designers: partitioned cache and randomized cache. In the last three years,...
Secure Computer Architecture in the Post-Meltdown World: A Long Road Ahead
The discovery of Meltdown and Spectre, along with their extensive media coverage, brought hardware security research to the spotlight. A wake-up call for major chipset manufacturers such as Intel, AMD, and ARM, we learnt that hardware vulnerabilities can be exploited...
Microarchitecture and Hardware Security Research at USENIX Security Symposium 2024
33rd USENIX Security Symposium was held in Philadelphia in August 2024. Following recent trends, the symposium featured several sessions dedicated to hardware and microarchitectural security. The program includes papers targeting side-channels and covert channels...