HPCA celebrated its 25th anniversary this year with significant participation of over 300 attendees! It was held in Washington D.C., USA between February 16-20.
Accelerators was a bigger theme this year (not only for ML but covering a broader range of domains including graph applications, bioinformatics, graphics, and virtual reality), where only one session (and a total of five papers, including one from an industry session and another one from CAL) represented security. Emerging technology sessions had more focus on processing near/in-memory and featured only one paper on quantum computing.
The technical program also included a variety of other sessions, ranging from the Best of CAL to the Industry session. All of which were well attended. HPCA-25 also hosted the very first Young Architect Workshop, “a forum for junior graduate students studying computer architecture and related fields to present early stage or on-going work and receive constructive feedback from experts in the field as well as from their peers”.
Best Paper Session
The best paper session featured four papers on four diverse topics.
The first paper, “The Accelerator Wall: Limits of Chip Specialization“, advocates that the benefits of specialization would diminish as technology scaling stagnates further, hence identifying specialization techniques making better use of an existing technology’s potential becomes more important.
The second paper, “Stretch: Balancing QoS and Throughput for Colocated Server Workloads on SMT Cores“, optimizes resource utilization by redistributing the slack from the latency-sensitive threads to the batch-processing ones, where running latency-sensitive and batch-processing threads together on SMT cores is a common practice. The result is a better trade-off (including both software/hardware complexity) without violating QoS of latency-sensitive threads. This paper got the best paper award.
The third paper, “CIDR: A Cost-Effective In-line Data Reduction System for Terabit-per-Second Scale SSD Arrays” proposes FPGA-based deduplication and compression for SSD arrays which performs better than compute-intensive software-based solutions and allows the system to adapt to different workload patterns at the same time.
The fourth paper, “Composite-ISA Cores: Enabling Multi-ISA Heterogeneity Using a Single ISA” introduces a novel aspect of single-ISA heterogeneity in multi-cores, where each core supports a subset of the very same ISA. Thereby microarchitectural specialization per core becomes possible without compromising binary compatibility.
The three industry sessions spanned “mobile and low-power”, “microarchitecture”, and “servers”, featuring an ML perspective paper from Facebook on inference at the edge.
Best of CAL
Best of CAL spanned three diverse topics: A hardware accelerator to detect ransomware attacks teamed with automated back-up control; the impact of cloud microservices on system bottlenecks and data center server design; and an analytical performance/energy/storage model which facilitates a more robust quantitative comparison between associative and conventional computing systems.
The first day started by the keynote by Srini Devadas from MIT, “Towards Secure High-Performance Computer Architectures”, which made the case for hardware-software codesign of processors from the ground up for security, specifically for disciplined microarchitectural isolation, via the use of a new abstraction: “enclaves”, i.e., processes that incorporate a specific security policy by construction.
Tuesday’s keynote, “When Moore met Feynman: Ultra-dense data storage and extreme parallelism with electronic-molecular systems” by Karin Strauss of Microsoft Research covered the potential and challenges of using synthetic DNAs for cold storage and how to perform computation on data stored in DNA using similarity search at scale as an example.
Wednesday’s keynote, “Rethinking Compilation in a Heterogeneous World” by Michael O’Boyle from the University of Edinburgh motivated hardware-defined software as an effective compiler paradigm as processors are becoming more and more heterogeneous — exploiting heterogeneity by mapping code regions to existing optimized libraries rather than building an optimizing compiler for each accelerator (or platform).
The Test of Time award went to “Dynamic Branch Prediction with Perceptrons” from HPCA-7 (2001) by Daniel Jimenez and Calvin Lin. HPCA-25 also featured an honor ceremony for the founding fathers, Laxmi Bhuyan, Dharma Agrawal, and (the first PC Chair) Yale Patt.
A panel on “How to improve HPCA”, moderated by Josep Torrellas from the University of Illinois took place on Tuesday evening, featuring Reetu Das from University of Michigan, Lisa Hsu from Microsoft Research, Ulya Karpuzcu from University of Minnesota, and John Kim from KAIST. The discussion spanned relevance to industry, scaling to a larger community, the range of topics, taking advantage of collocation with CGO/PPoPP, and the review process.
Highlights: Accepting more “idea” papers and papers on “building things”; having shorter presentations (of similar spirit as lightning talks), hence no parallel tracks; including retrospective talks from industry; exploring new and emerging application domains beyond ML; recording and posting talks; synchronizing breaks and avoiding topic overlaps in simultaneous sessions across colocated conferences; and not normalizing “survival of the fittest” mentality in the review process that justifies ethical compromise (when it comes to concurrent work, as a representative example).
While the focus was on HPCA, these suggestions equally apply to all three of the other architecture conferences, as well.
About the author: Ulya R. Karpuzcu is an associate professor from the University of Minnesota. The author would like to thank Ismail Akturk for contributions in this article.
Disclaimer: These posts are written by individual contributors to share their thoughts on the Computer Architecture Today blog for the benefit of the community. Any views or opinions represented in this blog are personal, belong solely to the blog author and do not represent those of ACM SIGARCH or its parent organization, ACM.