Like every other conference in the year 2021, thanks to the COVID-19 pandemic, MICRO-54 is once again being held in a virtual format over the Whova platform. While I miss the personal interactions you get with an in-person conference, I do appreciate the benefits of having a virtual conference, such as making it more widely accessible to people (both in terms of cost and travel). The proof is in the sauce. This year more than 1,068 people from 33 countries have registered to “attend” the conference.
MICRO-54 received 430 paper submissions with only 94 papers accepted for publication (22% acceptance rate), which is roughly on par with the number of papers submitted in 2020 but up 30% when compared to 2019.
For the 2nd time in a row general chair Dimitris Gizopoulos did a tremendous job guiding the organizing committee to have, once again, an amazing virtual International Symposium on Microarchitecture in its 54th year. This year’s Program Committee Chairs, Aamer Jaleel and Jishen Zhao, put together an innovative review process. The PC chairs goals were to tackle three main concerns regarding the review process: the randomness in the review assignments, the review quality, and accountability of reviews. With these goals in mind, Aamer and Jishen introduced many new features to the PC with some very impressive results, resulting in over 2000 reviews from 303 reviewers in total, and for the first time a reviewer award (keep reading to find out who got it). In addition to the creative review process, this year MICRO introduced for the first time an artifacts evaluation in which authors were allowed to submit their code for review and it also produced one new award category.
There were 18 paper sessions, with two running in parallel at all times, with an additional standalone session for the Best Paper nominees, for a total of 19 sessions and 94 papers. Roughly half of the submitted papers focused on accelerators and security, a quarter focused on traditional microarchitecture and memory systems and the rest were a mix between quantum, gpgpu, and other novel topics. Out of the 94 accepted papers, 23 took advantage of the artifact evaluation opportunity with 22 receiving badges for their codebase.
The program committee chairs, Aamer Jaleel and Jishen Zhao, implemented some creative approaches to address some of the concerns from the community regarding the review process. This year’s hotcrp interface included a hierarchical topic list to ease the burden of matching reviewers with papers, added review quality checks, and enabled a new channel of communication between reviewers and authors to clarify concerns after the rebuttal. The result of these processes was also measured with a survey in which authors had the opportunity to rate the reviewers. Survey average scores showed authors were mostly satisfied with the quality of the reviews and thought they had received constructive feedback. The average survey score on satisfaction was 3.6 out of 5. As a result of this impressive process, more papers were accepted compared to prior conference iterations, with 79 in 2019, 82 in 2020, and 94 this year – that is a 14% performance improvement!
The conference included some fun activities as well such as social gatherings in Gathertown, a virtual excursion to Athens, as well as a very entertaining panel discussion about microarchitecture research views from around the Globe. Panelists included community celebrities like Sarita Adve from University of Illinois, Onur Multu from ETH Zurich, Sreenivas Subramoney from Intel, Koji Inoue from Kyushu University and Per Stenström from Chalmers University.
In addition to the incredible program, the MICRO conference included for the third year in a row the Student Research Competition (SRC), in which students get to compete in undergraduate and graduate categories. On Wednesday the six finalists of the SRC got to present their work in front of the community and most importantly the judges.
Best Paper Session
There were four papers nominated for the best paper award. Zhiyao Xie, a PhD student from Duke University, presented his work “Apollo: Power Introspection for High Performance CPU” done in collaboration with ARM research. The second paper was “TIP: Time Proportional Instruction Profiling”, presented by Björn Gottschall, a PhD Candidate form Norges teknisk-naturvitenskapelige universitet (NTNU). The third presentation introduced “NDS: N-Dimensional Storage”, by Yu-Chia Liu a PhD student at University of California, Riverside. The final and fourth presentation was “GPS: A Global Publish Subscribe Model for Multi-GPU Memory Management” by Harini Muthukrishnan, a final year Ph.D. Candidate at the University of Michigan.
Kicking off each of the main conference days Tuesday through Thursday, a series of impressive keynote speakers enlightened us in their respective fields. In the Tuesday keynote, Michael T. Clark of AMD, who has contributed to every x86 processor from the K5 to the latest Zen generation, gave us an overview of his experience with designing high performance cores, giving historical perspective and context. On Wednesday, Professor Anastasia Ailamaki from the Computer Science department at EPFL, addressed the trade-offs between rigid device optimization and energy inefficient hardware oblivious systems. Dr. Ailamaki asserts that the balance between complexity and specialization is found in dynamic optimization of code paths during execution, called real-time intelligent systems. On the last day of the conference, Sean Lie, founder and chief hardware architect at Cerebras, presented the last keynote of the conference in which he described the process required to design the machine learning accelerator of the future which requires thinking outside the box and asserts that Moore’s law is not dead.
Workshops and Tutorials
Unlike prior versions, this year the workshops and tutorials were held on Monday before and Friday after the conference. This change was made after several people voiced concerns about these events being held during the weekend, which for a virtual conference, makes all of our personal lives more complicated than they need to be. This small change boosted event participation tremendously, with more than 250 people attending the events each day.
Among the workshops, there were some of the traditional players such as HASP, CWIDCA–formerly known as CWWMCA—and (NoCArc); as well as some newer ones such as the Cloud workshop by IBM Research and a DNN workshop by Facebook Research. The tutorials ranged from architectures geared towards RISC-V (GPGPU and SOC development), to hardware specializations, precision health and even hardware security.
The awards ceremony took place on Thursday, and it was kicked off with a special session to honor Guang Gao who passed away in September 2021. Dr. Gao had a prolific career in our community graduating 30 PhDs, mentoring 30 post docs, and many more significant contributions to compiler and microarchitecture instruction level parallelism and thread level parallelism. Dr. Gao received the Rau award in 2017.
Next in the award ceremony was the Best paper award, which due to the high quality of the papers, the 7 members of the selection committee decided to award a runner up paper in addition to the best paper award. The runner up award was given to “TIP: time proportional instruction profiling” by Björn Gottschall, Lieven Eeckhout, and Magnus Jahre; and the best paper award was given to “Apollo: Power Introspection for High Performance CPU” by Zhiyao Xie, Xiaoqing Xu, Matt Walker, Joshua Knebel, Kumaraguru Palaniswamy, Nicolas Hebert, Jiang Hu, Huanrui Yang, Yiran Chen, and Shidhartha Das.
The program committee chairs, Aamer and Jishen, created a new award for best reviews and awarded Saugata Ghose, Arthur Perais, and Jakub Szefer the Top Reviewer award of the program committee.
Samira Khan and Gennady Pekhimenko, the co-chairs for the artifact evaluation, presented the distinguished artifact award, which they clarified was an easy decision given that this work was highly ranked by all committee members. The award was given to “A Hardware Accelerator for Protocol Buffers” by Sagar Karandikar, Chris Leary, Chris Kennelly, Jerry Zhao, Dinesh Parimi, Borivoje Nikolic, Krste Asanovic, and Parthasarathy Ranganathan.
The SRC Competition first place winners were Shixin Song from the undergraduate group and Tarun Solanki from the graduate group.
Following the SRC winner announcements, Erik Altman introduced a record 10 inductees into the MICRO Hall of fame, which requires a minimum of 8 papers published at MICRO: Pradip Bose, Zeshan Chishti, Changhee Jung, Jeremie S. Kim, Hsien-Hsin Lee, Gilles Pokam, Xuehai Qian, Sreenivas Subramoney, Jun Yang, and Youtao Zhang.
Reetuparna Das presented the MICRO Test of time award, which this year was given to 2 prolific papers: “Razor: a low power pipeline based on circuit level timing speculation” by Daniel Jonathan Ernst, Nam Kim, Shidhartha Das, Sanjay Pant, Rajeev Rao, Toan Pham, Conrad Ziesler, David Blaauw, Todd M. Austin, Krisztián Flautner and Trevor N. Mudge; and to “Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction” by Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, and Dean Tullsen.
The B. Ramakrishna (Bob) Rau Award, which recognizes significant contribution to the community, was presented to Daniel Jimenez for his impact on neural branch prediction in microprocessors.
The business meeting was mostly an overview of the statistics and observations from the organizing committee. Timothy Sherwood also made an appearance to remind us that CARES is still present and available to anyone who would like to interact with them. CARES is also running an Inclusion and Diversity survey which the whole community should participate in. You can find the survey here: tinyurl.com/cares-micro21. Another important update, presented by Elba Garza, that came up from the business meeting is that CASA will be launching a new long term mentoring program called CALM and they are currently recruiting both mentors and mentees to participate. Click here if you are interested in participating in CALM. Finally the location for MICRO-55 has still not been determined and there is an active call for proposals to find the next organizer and location for MICRO-55. I get it, filling in Dimitris’ shoes seems like a significant challenge, but I am sure many of you out there can take on the challenge and succeed. I encourage you all to submit your proposals if you are interested in continuing the legacy of MICRO.
I would like to thank my amazing PhD students, Rhett Hanscom and Sylvia Llosa for helping me cover all the exciting events happening at MICRO 2021. Both of them attended various sessions and helped me write the article.
About the Author: Dr. Tamara Silbergleit Lehman is an Assistant Professor in the department of Electrical, Computer and Energy Engineering at the University of Colorado Boulder. Her research interests lie at the intersection of computer architecture and security.
Disclaimer: These posts are written by individual contributors to share their thoughts on the Computer Architecture Today blog for the benefit of the community. Any views or opinions represented in this blog are personal, belong solely to the blog author and do not represent those of ACM SIGARCH or its parent organization, ACM.