MICRO 2020, one of the flagship forums in the field of computer architecture, just came to an end in Athens, Greece. Hang on. We are still in the COVID-19 era, and I had to take a virtual, and the cheapest flight from New Delhi to Athens. The flight included access to the MICRO 2020 program as an online global event. It was attended by 1000+ attendees from 42 countries online.
MICRO 2020 received a record 446 submissions (30% more than 2019) and, in fact, more than ISCA 2020 (421 submissions). Some of the salient new things that the PC chairs, Mattan Erez and Jun Yang, tried are the following: (i) MICRO 2020 site did not mention the PC/ERC members and even the post-rebuttal discussions were anonymous, and identities of the PC/ERC members were disclosed just two days before the PC meeting, and (ii) Most rated top reviewer award based on authors’ votes was refreshing. More about the PC meeting by Jun Yang and Mattan Erez can be found here.
Workshops and Tutorials
MICRO featured an excellent set of workshops and tutorials spanning different fields. Tutorials included researchers from Georgia Tech explaining their data-centric approach using MAESTRO for mapping DNN workloads to DL accelerators, a tutorial on DSAGen by researchers from UCLA, a tool to automatically generate spatial accelerators for a given application, and a tutorial on ESP from Columbia University, an open-source automatic integration framework for building/prototyping heterogeneous SoCs. Key workshops included JOBS, a unique and well-received attempt to accelerate the job search for computer architecture researchers, the uArch workshop, with a specific focus on promoting research for undergraduate students, and CWWMCA focusing on women and minorities in Computer Architecture. Apart from the workshops and tutorials, MICRO-53 had “meet a senior architect” and “meet a senior Ph.D.” that are quite regular with ISCA.
Around 10% of the submitted papers belong to microarchitecture followed by a broad theme of accelerators, ML accelerators, and domain-specific architectures; then, Memory systems: cache and DRAM, and then security and privacy. Security tracks featured papers mostly from the defensive side except for PTHammer (a row-hammer family of attack hammering page tables). In microarchitecture tracks, too, ML techniques played a role. The ML accelerators track featured a broad set of proposals spanning across tasks for both training and inference. A key percentage focused on exploiting sparsity to accelerate ML. There was also a session dedicated for accelerators with emerging technologies. The papers in Domain-Specific Architectures focused on graph applications and genomic sequencing. One of the welcome trends with MICRO-53 was that many papers had open-sourced their implementations.
Keynote 1: The MICRO 2020 main program started with a keynote of Why IoT is hard? by Rich Wolski. The talk was about a software framework that mitigates the challenges. The highlight of the talk was CSPOT, a serverless software platform of things. Some of the punchlines and key takeaways are “not big data but big little data,” and “build repurpose-built instead of purpose-built.”
Keynote 2: The day-2 keynote from Christina Silvano was on a timely topic describing Exscalate4CoV European Project and the role of exascale platforms in handling pandemics like COVID-19. The talk highlighted how supercomputers in Europe played a significant role in finding drugs for COVID-19.
Keynote 3: The day-3 keynote was by Srilatha (Bobby) Manne on architecting a sustainable planet. She highlighted that data centers consume 205 Twh of electricity/year and how our daily usage of mobile-apps (Netflix, Facebook, etc.) contributes immensely to carbon-emissions, which she alluded to as “Death by a billion swipes.” She also highlighted the benefits of hyperscale data centers to reduce carbon footprints. She then broke down the carbon-emission on the data-centers and stressed the need to perform demand shaping. She finally motivated the need for having sustainable data centers through sustainable silicon.
The best paper award was given to Bit-Exact ECC Recovery (BEER) by Patel et al. from ETH Zurich. BEER introduces novel testing and profiling methodology to determine the working of proprietary on-die ECCs, a closely guarded trade secret — enabling researchers to perform reliability studies on commodity DRAM devices. The runner-up was given to Duckering et al. from the University of Chicago. They propose a 2.5D memory architecture using qubits that can efficiently implement error-correcting algorithms to improve the reliability of qubit memories to enable quantum computing. Other best-paper nominees include DStress, from Mukhanov et al., an automatic framework based on Genetic Algorithms to generate stress tests to evaluate DRAM reliability, and the work of Jie et al. that rethinks tiling and loop-fusion transformations to optimize the memory hierarchy.
The ACM SRC featured some of the exciting topics of research done by undergraduate and graduate students. Peng Gu won the 1st prize in the graduate category for DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads. In the undergraduate category, Guyue Huang won the 1st prize for Towards Fast Graph Neural Network Training with Efficient and Framework-Compatible Sparse-Dense Matrix Multiplication.
Jorge Albericio, Rakesh Kumar, Jason Mars, Lingjia Tang, and Thomas Wenisch were inducted into the MICRO hall of fame for reaching the 8 MICRO papers mark. The final award was the prestigious B. Ramakrishna Rau award, established in the memory of Bob Rau, and awarded to people with substantial contributions in the field of computer microarchitecture and compiler code generation. André Seznec received the award with the apt citation “For the pioneering contributions to cache design and branch prediction.” Certainly, he has made some foundational contributions in both the fields with Skewed-Associative Caches and TAGE family of predictors, among many others. He gave a heart-warming speech about his journey in the architecture world while pouring words of wisdom along the way. His friendly banter on branch-prediction and him acknowledging his fierce competitors highlight how much he has enjoyed the process of invention – looking forward to his inspiring video being posted.
The business meeting was mostly focused on the logistics for the future MICROs, especially the duration of MICRO. One of the topics of discussion was to conduct talks twice with a 12-hour gap so that people can try to attend at least one of the slots. SIGMICRO has a new team headed by Onur Mutlu with a new agenda to popularize the field of microarchitecture. Students can join for free. So if you are a student, then do not miss this opportunity and join today. MICRO-54 will be held in Athens, and Dimitris Gizopoulos will be the general chair again.
Similar to “virtual memory abstraction,” an attendee can feel like s(he) can watch (virtually attend) all the talks and interact with all the attendees. The Whova platform provided the best virtual conference experience. One of the issues that is unavoidable is the global clock. For example, the business meeting went on post-mid-night for attendees in India, and of course, very late-night for countries like China and Australia.
Although in-person conferences are more lively and engaging, virtual conferences are a blessing in disguise for motivated students and faculty members from different parts of the world who generally cannot travel to attend it in-person. I would expect that such a democratization of access to a wide set of people might lead to more ideas and breakthroughs in the years to come. In the future, even after things get back to normal — which is what we are all badly hoping for — it would be appreciated if the conference organizers considered having additional virtual access to the conference sessions and discussions. Hope to see you all in Athens for MICRO-54. Stay safe and stay healthy.
I would like to acknowledge the help of Vinod Ganesan for this article. There were many parallel tracks to attend, and it was overwhelming. Vinod kindly attended the parallel tracks, and discussed happenings/insights, and helped me write this article by putting forth his thoughts wherever appropriate.
About the author: Biswabandan Panda is a member of the faculty at the Computer Science and Engineering Department, IIT Kanpur. His research interests span microarchitecture for performance and security.
Disclaimer: These posts are written by individual contributors to share their thoughts on the Computer Architecture Today blog for the benefit of the community. Any views or opinions represented in this blog are personal, belong solely to the blog author and do not represent those of ACM SIGARCH or its parent organization, ACM.