by David Patterson and Andrew Waterman on Sep 18, 2017 | Tags: Architecture, CPU, ISA, Parallelism
In the process of writing a short introduction to RISC-V, we compared RISC-V vector code to SIMD. We were struck by the insidiousness of the SIMD instruction extensions of ARM, MIPS, and x86. We decided to share those insights in this blog, based on Chapter 8 of our...
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