Archive of posts tagged: Architecture
Distance-Based ISA for Efficient Register Management
CPU cores have become significantly wider over the past decade. Ten years ago, the highest-performance CPUs could decode only up to four instructions simultaneously and execute up to eight instructions. However, top-tier CPUs released in recent years have grown to...
Reducing Embodied Carbon is Important
A recent post raises awareness of the challenges of reducing operational carbon, while also controversially challenging the importance of embodied carbon. We rebut the arguments raised against using embodied carbon as a design metric and conclude by advocating for more research on reducing embodied carbon.
Emerging Fault Modes: Challenges and Research Opportunities
Overview Reliability is essential for computing. However, as technology nodes have scaled, there have been several fundamental physical challenges to overcome to provide the abstraction of reliability. One such challenge has been the emergence of marginal...
Current status, needs, and challenges in Heterogeneous and Composable Memory from the HCM workshop (HPCA’23)
Introduction Memory systems are evolving into heterogeneous and composable architectures. Heterogeneous and Composable Memory (HCM) offers a feasible solution for terabyte- or petabyte-scale systems, addressing the performance and efficiency demands of emerging...Subscribe
