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If you needed proof that the Golden Age of Computer Architecture is here, MICRO 51 was it. The technical program was a glowing reflection of the community as we venture forward into new and familiar computing territories.

This year MICRO was in Japan, led by general chairs Mark Oskin and Koji Inoue. Fukuoka is a modern, sunny, coastal city filled with some of the nicest, most welcoming, and polite people I’ve ever met. At last year’s MICRO, there was an air of tension as the long overdue discussion of antiquated, opaque community standards and processes as well as our disgracefully undiverse and gender imbalanced community was finally set to take place. With a statement from Margaret Martonosi and packed business meeting, the overhaul of MICRO’s practices began. As Boston was a fitting city to ignite change, so too was Fukuoka in constructing a welcoming and constructive community. The city’s positive personality was contagious and seemed to have an observable effect on the conference. With the passing of a year, progress has been made toward improving matters. MICRO passed bylaws, has a new steering committee, continues to host the Women and Minorities in Computer Architecture workshop, made available “Diversity Ally” badge identifiers, and established CARES. Wen-Mei Hwu led the business meeting discussion where he presented the bylaws and their implications, fielding questions from the audience. Things generally went smoothly. However, the results of the diversity survey reminded us that we, as a community, still have a long way to go to make things right.

Workshops and tutorials

The weekend preceding the conference was pack with material spanning the compute stack. Sessions on quantum and photonics showcased state-of-the-art research and outstanding challenges while teaching the basics of the newer technologies in an architecture-friendly way. Tutorials on dynamic binary translation and design margins for multicore CPUs were filled with material to ramp up researchers on the topics and use available tools. The 11th installation of NoCArc was held along with the first workshop on domain specific system architecture.

Brandon Lucia and his lab at CMU got things started with a tutorial on intermittent computing. They hit on the challenges of processing without a reliable or consistent power source and distributed homemade development boards for attendees to get some hands-on experience.

The next day the now annual RISC-V Day workshop was organized by Shumpei Kawasaki and Krste Asanovic. Krste got the day going by introducing RISC-V and their vision for AI. The room was packed and sported a healthy mix of industry and academic attendees. The RISC-V community has grown to the point that this year there was a separate RISC-V tutorial on software-defined architecture.

The Women and Minorities in Computer Architecture workshop also took place on Sunday. It concluded with a panel session where Jamie Moreno tasked everyone to take meaningful action to improve community diversity, especially in encouraging graduate studies.

The day concluded with a panel session from Intel and the NSF. Panelist hinted that there may be more remaining performance to be eked out from ILP than the community thinks and spoke about potential funding opportunities and new tools.


Dr. Satoshi Matsuoka of RIKEN kicked off the main program with a keynote titled “From Post-K onto Post-Moore is from FLOPS onto BYTES, and from Homogeneity to Heterogeneity”. The K machine came online in 2017 and is #16 on the Top500 list. The talk echoed the importance of co-design and encouraged researchers to focus on all aspects of ML: data, algorithms, and systems. Matsuoka explained the design of the Post-K machine — the Japanese ARM-based exascale supercomputer designed for data-parallel training with asynchronous gradient updates. Post-K will also be chalked full of flops, likely placing high on the Top500. As the title suggests, it also has a focus on achievable performance rather than raw flops alone, even including support for INT8 and INT16 formats. Matsuoka claimed that continued performance scaling will require innovation in performance modeling, interconnects, and specialization.

The timely keynote, “Security Aware Microarchitecture Design”, was given Tuesday morning from Professor Ruby Lee of Princeton. She offered three design rules to enable secure processors: accesses should not occur without authorization, no observable effects of microarchitectural changes or aborted execution, and do not allow interference through shared resources or else the signals should be made indistinguishable through randomization. The MICRO audience was motivated to develop automated checking for security design rule violation before integrating new microarchitectural features. Looking forward, Lee concluded by saying machine learning could be a powerful tool for improving security.

Mike Davies, Intel’s neuromorphic computing program leader, spoke of the performance and efficiency potential that neuromorphic approaches promise by more closely imitating biological systems. He hit on key principles include fine-grained parallelism, event-driven computation, and low-precision and stochastic representations. Intel’s Loihi is a fully digital implementation of a spiking neural network using an event-driven, asynchronous, many core architecture design. Both Loihi and IBM’s True North implement an extended integrate-and-fire neuron model, though Loihi claims to be more programmable. Loihi also supports online learning and is able to dynamically adapt, fitting for a brain-inspired processor!

Conference themes: AI, security, and everything in-between

MICRO had an exceptionally strong program this year, thanks to the program co-chairs Hyesoon Kim and Sudhakar Yalamanchili. The traditional tracks included work on TLBs, register renaming, and memory compression [1, 2]. Many now cornerstone tracks including accelerators, near memory computing, and GPUs covered topics spanning graph processing, dynamic parallelism, NUMA performance on multi-GPU systems, and a processing in DRAM.

In 2016 when someone asked me “Are we really going to have 6+ MICRO papers a year on hardware support for AI/ML?”. I said no, I think it’s just this year and after there will likely be 3-5 per major conference. I was wrong; there were 12 papers on machine learning this year. Moreover, the trend does not appear to be slowing as it seems more than half the community is at least tangentially involved in a ML project.

While MICRO had a record number of ML papers (6 in 2016 and 4 in 2017), it didn’t feel overwhelming and attendees didn’t groan about “AI fatigue”, at least not openly. This year there was a distinct focus on the practical problem of distributed training and new ML applications. Moreover, of the training papers, many proposed PIM based solutions or considered emerging memory technologies.

Another reason there was less languor surrounding ML was that security was the clear “hot topic”. And it was fitting for MICRO, which also happened to be the first major conference deadline after the Spectre and Meltdown attacks were announced. With these recent, ominously named exploits, designing secure processors forces us to rethink many of the microarchitectural optimizations made for the sake of performance. Fittingly, Moin Qureshi’s single-author paper “CEASER: Mitigating Eviction-Based Cache Attacks via Dynamically Encrypted Address” won the best paper award.

Another notable theme this year was new computing paradigms. In particular, there were papers on intermittent and quantum computing. While the ‘hype’ of Security and ML may have inescapably been on most attendees minds, published work looked to be among the first to explore these challenging directions that will be necessary for the (more distant than ML and security but not so distant from the final end of Moore’s law) future.


Dr. Ravi Nair from IBM was this year’s Bob Rau award winner. He began and concluded his talk by sharing the importance of family, ethics, and the need to be more than just a good researcher. Nair presented data to instill the harsh financial realities of early technology adoptions, and how he thought this would necessitate more cost-saving automation work like the PICO project. Three Test of Time awards went to: “Assigning Confidence to Conditional Branch Predictions” [1996], “Efficient Path Profiling” [1996], and “DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design” [1999]. When asked to comment on DIVA, Todd shared: “A rule-breaking approach to research is an effective one (DIVA broke the rule that all bugs need to be found). Industry can like and support an idea with no intention of ever using it”.

This year Alper Buyuktosunoglu, John Kim, Tao Li, Vijay Janapa Reddi, Daniel Sanchez, Yiannakis Sazeides, and Chris Wilkerson were inducted into the MICRO Hall of Fame.

About the author: Brandon Reagen is a research scientist at Facebook.

Disclaimer: These posts are written by individual contributors to share their thoughts on the Computer Architecture Today blog for the benefit of the community. Any views or opinions represented in this blog are personal, belong solely to the blog author and do not represent those of ACM SIGARCH or its parent organization, ACM.