DNN Accelerator Architecture – SIMD or Systolic?
While the concept of hardware acceleration has been around for a while, DNN accelerators are perhaps the first to see the light of commercial adoption due to the AI/ML wave. Giant software corporations, veteran hardware companies, and a plethora of start-ups have...
Mobile SoCs: The Wild West of Domain Specific Architectures
The Moore’s Law engine that we have come to depend upon is sputtering. It is encouraging architects to innovate in alternative ways to keep the industry moving forward. The most widely accepted approach is using domain specific architectures, and as such, in recent...
Data management on non-volatile memory
In a recent blog post, Steve Swanson presented three milestones that mark the adoption path of non-volatile memory by applications. The next step in this path is tailoring fundamental protocols and algorithms for non-volatile memory. We illustrate this point using...
Chilly Climate in Computer Architecture?
To better understand the climate of the computer architecture community and assess initiatives launched by WICARCH, we conducted a survey from mid-June to mid-July. The survey followed several efforts to understand gender diversity in computer architecture and the...
Sacrificing Interoperability for Information Security: Containing Data Loss and Malware Propagation
Using hardware that does not provide software and data interoperability could address security problems.
How to be a good PC member ……. not!
Here are some tips to be a good PC member.
Server Architecture for the New Age Datacenter
Server architectures have largely been boring. Boring has been good. It has helped applications thrive in a stable H/W ecosystem and innovate at providing business logic. While performance improvements have largely been single thread performance improvements extended to data center class systems, we are beginning to see a new era in Server architecture designs driven by memory technologies, accelerators and fabrics like Gen-Z, CCIX and Open CAPI that glue them.
Keywords
X86, Memory centric architectures, Gen-Z, CCIX, Open CAPI
The von Neumann Bottleneck Revisited
The term “von Neumann bottleneck” was coined by John Backus in his 1978 Turing Award lecture to refer to the bus connecting the CPU to the store in von Neumann architectures. In this lecture, he argued that the bus was a bottleneck because programs execute on the CPU...
Easy Persistent Memory Performance Wins
Mainstream non-volatile main memory (NVMM) is just around the corner: Intel is opening up access to their 3DXpoint technology to a broader range of companies, and we are gradually learning more about the technology. Despite our growing understanding, the question of...Subscribe
